vhdl Ram block not compiled and fitted as such

[Altera_Forum]

Basically i have written my own simple ram block in vhdl, which is dual port which the cyclone 2 should easily be able to happen. however whenever i compile and fit it the software just puts it into LE rather than dedicated ram, which obviously is not what i intentioned, what possible could i be doing wrong (something in the options which are all currently at default) that is causing it to do this? 

 i am using quartus 2 web edition, and modelsim altera edition

[Altera_Forum]

First check that you are using the correct coding style for dual-port RAM. I think support for inferred true dual ports is fairly new. (Maybe what's new is for dual-clock true dual ports--I don't remember.) It's probably covered in the Quartus handbook, most likely in the chapter referenced at http://www.alteraforum.com/forum/showthread.php?p=3369#post3369.

[Altera_Forum]

Also in the Quartus VHDL/Verilog editor, go to Edit -> Insert Template -> Full Designs, and there should be some RAM examples.

[Altera_Forum]

Posting your source code or a relevant snippet would be helpful, too. :)

[Altera_Forum]

Hello, 

 I think, not all types of dual-port ram can be inferred from HDL. It could be easier to use a megafunction instance. Cause "dual-port from HDL" wasn't supported in previous Quartus versions, I have megafunctions instances in most designs with dual-port, for special constructs, e. g. with different port widths, you need megafunction anyway.   I noticed, that Altera IP typically uses megafunction instances even for single port RAM/ROM.  Regards, Frank

[Altera_Forum]

thank you all for the help 

 i looked at the templates for the ram and found out the problem, it was an unfortunate error due to some idiotic coding by me, but all is sorted and working nicely :)