NCONT ERROR in ACK for access 0 : ACK = 0x01 when trying to connect with Arm DS debugger through JTA

[Richard_P]

Hi,

I am an embedded developer trying to help bring up a custom Arria 10 board. I can successfully load the SOF file to configure the FPGA using the Intel Quartus Prime Programming utility through a USB Blaster 1 connected to the JTAG interface, but when I try to manually load and run the preloader using the Arm DS debugger I get the "NCONT ERROR in ACK for access 0: ACK = 0x01" message in the Target Console window. From what I have read on the forums, this indicates that there is a JTAG COM issue with the board. I have consulted with our FPGA designer and board layout person, and they tell me the JTAG interface is configured and connected correctly. I tend to believe them since I can successfully load the SOF file through the JTAG interface. After getting the error, the debugger pops up a window stating "The target hardware identity could not be verified. Please check that the target being connected to is of type Arria 10 SoC". I have found a similar post on the Arm DS support website regarding this issue and followed the bare-metal user guide procedure for loading the preloader which worked for that person, but it did not work for me. The preloader instructions can be found at https://www.intel.com/content/www/us/en/docs/programmable/683211/current/import-preloader.html. Any help or suggestions with this issue would be greatly appreciated. 

Thanks,

Richard

[aikeu]

Hi Richard_P,

May I know how you build your project where you able to obtain the preloader?

https://github.com/altera-opensource/intel-socfpga-hwlib

https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10

Are you able to run some of the example exercise in from the link below using a prebuilt files?

https://www.rocketboards.org/foswiki/Documentation/SoCEDS

Thanks.

Regards,

Aik Eu

[Richard_P]

Hi Aik,

Thank you for your response. I am obtaining and building the preloader using the RocketBoards link to BuildingBootloaderCycloneVAndArria10. Specifically, I am following the Arria 10 SoC- Boot from QSPI directions since we are using QSPI flash. I am building on a Linux Host - Ubuntu running on a Windows machine. I use the hps.xml output file from our custom FPGA design and everything builds cleanly. When I try to connect and load the preloader through the Arm DS debugger I get the "NCONT ERROR in ACK". I get the same error when trying to connect and debug the HelloWorld examples that are part of the Intel SoC EDS. Could this be a USB Blaster issue possibly? How can I go about diagnosing the cause of the "NCONT ERROR in ACK" message?

Thanks for your help.

-Richard

[aikeu]

Hi Richard_P,

Are you running Arria 10 SoC - Debugging U-Boot from the link below?

https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10#Appendix_45_Debugging_U_45Boot_with_Arm_DS_Eclipse

I think can check if your board got problem booting into the Uboot user space with UART logs without any armds involvement first.

Below are the necessary files to be flashed(refer document) into qspi flash at different addresses:

~/intelFPGA_pro/23.2/nios2eds/nios2_command_shell.sh \

quartus_hps -c 1 -o pv -a 0x0000000 u-boot-splx4.sfp

~/intelFPGA_pro/23.2/nios2eds/nios2_command_shell.sh \

quartus_hps -c 1 -o pv -a 0x0100000 fit_uboot.itb

~/intelFPGA_pro/23.2/nios2eds/nios2_command_shell.sh \

quartus_hps -c 1 -o pv -a 0x0300000 fit_spl_fpga.itb

*u-boot-splx4.sfp (FSBL)

*fit_uboot.itb (To enter Uboot user space)

*fit_spl_fpga.itb (Required to allow HPS DDRAM to be brought up, and must do be done in SPL)

Thanks.

Regards,

Aik Eu

[Richard_P]

Hi Aik,

Yes, I was following those instructions for debugging uboot with Arm DS. I did try flashing the spl and uboot images to the QSPI flash with the quartus_hps utility but that did not work either. I got the following error messages every time tried to flash anything:

    Error: send_access_data() error while accessing DP Register

    Error : Fail to power down the System and Debug power

This might be a separate problem. The original reason I was trying to load and run the preloader and uboot through the Arm DS debugger was because our QSPI Flash (Micron MT25QU02G) was not ready at the time. It's supposed to be ready to use now though, but maybe not after seeing these error messages.  If this is a separate problem, I still need to resolve the debugger error because I will need debug capability for application development.

Since I am working with a custom FPGA and board design and not a dev kit design and board where everything is preset, are there security settings I need to check or set to enable JTAG debugging or flash programming for the Arria 10?

Thanks,

Richard

[aikeu]

Hi Richard_P,

For Arria10 development kit, there is no specific settings required as I know of to enable jtag and programming.

Basically switching the kit to qspi flash daughter card will tell the system to boot up from qspi flash.

I think can check and verify the below:

Is running jtagconfig working without issue on your computer?

Running auto detect in quartus programmer GUI will able to detect connected devices?

For QSPI flash related, can try to check and verify some of the cmds use, example like read silicon ID of the flash

You can speculatively use --boot=18 option in quartus_hps command line to see if it helps.

https://www.intel.com/content/www/us/en/docs/programmable/683039/21-3/hps-flash-programmer.html

Thanks.

Regards,

Aik Eu

[aikeu]

Hi Richard_P,

May I know is there any follow up from the previous comment?

Thanks.

Regards,

Aik Eu

[Richard_P]

Hi Aik,

1) Regarding the jtagconfig, yes it seems to be working fine. He is the output I get:

$ jtagconfig
1) USB-Blaster [USB-0]
02E050DD 10AS066H(1|2|3|3E2|4|4E2)/..
4BA00477 SOCVHPS

Here is the output with the --debug option:

$ jtagconfig --debug
1) USB-Blaster [USB-0]
(JTAG Server Version 20.1.0 Build 177 04/06/2020 SC Pro Edition)
02E050DD 10AS066H(1|2|3|3E2|4|4E2)/.. (IR=10)
4BA00477 SOCVHPS (IR=4)

Captured DR after reset = (02E050DD4BA00477) [64]
Captured IR after reset = (1551) [14]
Captured Bypass after reset = (0) [2]
Captured Bypass chain = (0) [2]

2) The Quartus Programmer Utility detects both devices (see attached image).

I can load the SOF through the JTAG port using Quartus Programmer to configure the FPGA without any problems (see attached image). But after that, when I try to use the quartus_hps utility to erase or program the flash I get the following error:

$ quartus_hps -c 1 -o E
Info: *******************************************************************
Info: Running Quartus Prime Programmer
Info: Version 20.1.0 Build 177 04/06/2020 SC Pro Edition
Info: Copyright (C) 2020 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and any partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel FPGA IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
Info: Intel and sold by Intel or its authorized distributors. Please
Info: refer to the applicable agreement for further details, at
Info: https://fpgasoftware.intel.com/eula.
Info: Processing started: Mon Oct 16 16:48:51 2023
Info: System process ID: 48860
Info: Command: quartus_hps -c 1 -o E
Current hardware is: USB-Blaster [USB-0]
Found HPS at device 2
Double check JTAG chain
HPS Device IDCODE: 0x4BA00477
Error: Fail to reset Debug
Error: Quartus Prime Programmer was unsuccessful. 0 errors, 0 warnings
Error: Peak virtual memory: 115 megabytes
Error: Processing ended: Mon Oct 16 16:48:54 2023
Error: Elapsed time: 00:00:03
Error: System process ID: 48860

Any ideas as to why the JTAG port to the FPGA seems to work just fine, but not to the HPS?

Thanks for your help.

-Richard

[aikeu]

Hi Richard_P,

For Cyclone V qspi booting.

https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10#Cyclone_V_SoC_45_Boot_from_QSPI

Can check if the BSEL is selected as below:

Set BSEL jumpers to boot from 3.3V QSPI device:

• BOOTSEL0 (J28): left
  • BOOTSEL1 (J29): left
  • BOOTSEL2 (J30): left

Try to run "qaurtus_hps -c 1 -b 18 -o s" to perform cold reset and read the silicon id of the qspi flash.

Thanks.

Regards,

Aik Eu

[Richard_P]

Hi Aik,

I tried your suggestion and this is what I got:

$ jtagconfig
1) HAN Pilot Platform [USB-1]
02E050DD 10AS066H(1|2|3|3E2|4|4E2)/..
4BA00477 SOCVHPS

2) USB-BlasterII [USB-2]
02E050DD 10AS066H(1|2|3|3E2|4|4E2)/..
4BA00477 SOCVHPS

Engineering@ENG92 /cygdrive/c/intelFPGA_pro/20.1/embedded
$ quartus_hps -c 2 -b 18 -o S
Info: *******************************************************************
Info: Running Quartus Prime Programmer
Info: Version 20.1.0 Build 177 04/06/2020 SC Pro Edition
Info: Copyright (C) 2020 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and any partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel FPGA IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
Info: Intel and sold by Intel or its authorized distributors. Please
Info: refer to the applicable agreement for further details, at
Info: https://fpgasoftware.intel.com/eula.
Info: Processing started: Fri Oct 20 20:15:23 2023
Info: System process ID: 24228
Info: Command: quartus_hps -c 2 --boot=18 -o S
Current hardware is: USB-BlasterII [USB-2]
Hardware frequency: 6000000
Found HPS at device 2
Double check JTAG chain
HPS Device IDCODE: 0x4BA00477
Error: Fail to reset Debug
Error: Quartus Prime Programmer was unsuccessful. 0 errors, 0 warnings
Error: Peak virtual memory: 116 megabytes
Error: Processing ended: Fri Oct 20 20:15:26 2023
Error: Elapsed time: 00:00:03
Error: System process ID: 24228

No change in behavior it seems. I hooked up our Arria 10 HAN Pilot dev kit and I also cannot connect the Arm Development Studio debugger to load the preloader described in the Intel examples. I can program the HAN Pilot dev kit SOF file successfully through the JTAG port just like I can do with our custom board though. So, the cause of my HPS JTAG problem is not the new custom board design since the dev kit board has the same issue. So, I suspect I have a Blaster communication issue or perhaps an Arm Development Studio debug configuration issue. I have upgraded to an Altera Blaster II by the way but it does not behave any differently than the previous Blaster I. I have checked my Arm DS debugger configuration and it is consistent with the Arria 10 example programs. I'm stuck on this issue and it is preventing the project from moving forward. I think my next step is to request direct Intel support unless you have any other suggestions. Thanks for your help.

-Richard

[aikeu]

Hi Richard_P,

I was not able to see the problem "Error: Fail to reset Debug" on the board on my side. For Arria10, the command "qaurtus_hps -c 1 -b 18 -o s" can be issued without problem regardless of involving qspi flash or not. If cannot work, try to power off and power on the board again after a while and run the command again.

Anyway I see you connect two jtag cable at the same time. Just to avoid jtag cable selection confusion in the attempt with cable selection(quartus_hps -c 1/quartus_hps -c 2) , allow only one jtag connection at one time.

The problem is not due to Arm ds debugger configuration but is the on HPS side of the board and fpga side is working fine because the .sof file can be flashed.

Thanks.

Regards,

Aik Eu

[aikeu]

Hi Richard_P,

May I know any follow up from the previous comment?

Thanks.

Regards,

Aik Eu

[Richard_P]

Hi Aik,

I will remove the other Blaster just in case. I would like to focus testing on the dev kit for now that that would eliminate any custom board issues. Using the dev kit, I am not able to successfully perform the steps outlined in the "Run U-Boot SPL from Debugger" section of the "SoCEDS and ARM Development Studio" instructions found on RocketBoards here: SoCEDS and ARM Development Studio | Documentation | RocketBoards.org

I am unable to connect to our dev kit board using the Arm Development studio debugger. I get the This same "NCONT ERROR in ack" message that I get with our custom board when the debugger tries to connect through the JTAG interface. I can successfully program the FPGA with the dev kit design SOF though, just like with our custom board.

I wanted to ask if you can try and duplicate my dev kit setup as best you can and execute the "Run U-Boot SPL from Debugger" instructions from the RocketBoards website and see what results you get.

I am using the HAN Pilot Platform dev kit (Terasic - All FPGA Boards - Arria 10 - HAN Pilot Platform). It has an on-board USB Blaster II that is connected to a PC running Windows 10 Pro (Ver 22H2, OS Build 19045.2965) with an Intel Core i7 processor (3.40GHz) and 16GB of RAM. The dev kit board is currently configured to boot the default Linux from the Micro SD card.

I'm not sure if you have access to that particular dev kit, but hopefully you have access to the more common Intel Arria 10 SX SoC Development Kit. That dev kit is similar. Are you able to try and execute the "Run U-Boot SPL from Debugger" instructions on an Arria 10 dev kit?

Thanks,

Richard

[aikeu]

Hi Richard_P,

I will close this thread if no follow up.

Thanks.

Regards,

Aik Eu

[Richard_P]

Hi Aik,

It looks like we were posting at the same time. I was asking in my post above yours to see if you can duplicate my error with an Arria 10 dev kit if you have access to one.

Thanks,

Richard

[aikeu]

Hi Richard_P,

Sorry for late reply. I have tested with the Arria10 Soc Dev kit before. There was no connection error issue when working with it. I think the problem might due to your physical board settings. Example can check if there is any default switches/jumpers settings change from the user guide refering to the link below:

https://www.intel.com/content/www/us/en/docs/programmable/683227/current/soc-development-kit-overview.html

Thanks.

Regards,

Aik Eu

[aikeu]

Hi Richard_P,

Another thing to check is the board is still able to boot up where HPS can run without issue using the GSRD.

Can just download the image file and write to a SD card for the board to boot up and see if there is issue from the UART logs.

https://www.rocketboards.org/foswiki/Documentation/Arria10SoCGSRD#Creating_SD_Card

Thanks.

Regards,

Aik Eu

[aikeu]

Hi Richard_P,

I am closing this thread for now as I was unable to reproduce the issue on my side. Do consider to contact Terasic for any hardware related issue with Han Pilot board. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Thanks.

Regards,

Aik Eu