Compute in data streaming accelerator

asdasf · ‎01-17-2026

Hi,

I am currently trying to use the Data Streaming Accelerator (DSA) to (1) read two inputs, (2) do XOR, and (3) store the outputs.

According to the “Intel® Data Streaming Accelerator Architecture Specification (v3.0)”, this kind of compute operation appears to be supported by the hardware.

However, when using the Intel Data Movement Library (DML) or when using DSA directly via idxd.h, I cannot find any interface for XOR operations -- only memory copy, memory fill, ...

Are the compute operations described in the DSA architecture spec currently unavailable in software stacks?

If they are available, is there any guideline, header, or example for using them?

Thanks.

// idxd.h

/* Opcode */

enum dsa_opcode {

DSA_OPCODE_NOOP = 0,

DSA_OPCODE_BATCH,

DSA_OPCODE_DRAIN,

DSA_OPCODE_MEMMOVE,

DSA_OPCODE_MEMFILL,

DSA_OPCODE_COMPARE,

DSA_OPCODE_COMPVAL,

DSA_OPCODE_CR_DELTA,

DSA_OPCODE_AP_DELTA,

DSA_OPCODE_DUALCAST,

DSA_OPCODE_TRANSL_FETCH,

DSA_OPCODE_CRCGEN = 0x10,

DSA_OPCODE_COPY_CRC,

DSA_OPCODE_DIF_CHECK,

DSA_OPCODE_DIF_INS,

DSA_OPCODE_DIF_STRP,

DSA_OPCODE_DIF_UPDT,

DSA_OPCODE_DIX_GEN = 0x17,

DSA_OPCODE_CFLUSH = 0x20,

};

Poojitha · ‎01-18-2026

Hi asdasf,

Greetings for the day!

Thank you for reaching out to Intel Support. We acknowledge receipt of your concern and would like to assure you that assisting you is our top priority.

To assist you further, we require some additional information from your end.

Kindly provide the system details and the processor model for which you are seeking the necessary information.

This will help us review the complete details and assist you further.

We appreciate your understanding!

Best regards,

Poojitha N

Intel Customer Support Technician