Intel IO Margin for Sapphire Rapids

[junhee]

I did test IO margin PCIe Gen3 device on Sapphire Rapids, and got a result. 

For PCIe Gen4 and Gen5, a  Lane margining is that number of volage step range, min 32 ~ max 127 and number of time step range, min 6 ~ max 63. 

I'm wonder what is the margin range for Gen3. Is it same range like Gen4/5 ?

for example, I got a IO margin data of Gen3.
lane0 : voltage (high 121, low -120), timing (26.4)

[JosueO_Intel]

Hello junhee,

Thank you for posting on the Intel communities. 

It is important for you to know that for these unreleased products, you should contact Intel® SDP support, you can access their support site here:

 http://www.intel.com/sdp

Hope this information is useful, if you need any additional information, please submit a new question as this thread will no longer be monitored.

Regards,

Josue O.  

Intel Customer Support Technician