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Hi all,
I’ve been experimenting with Intel’s PCM tool to monitor CXL memory traffic on a 4th Gen Xeon (Sapphire Rapids) system.
Here’s what I observed:
Write bandwidth to a CXL memory device can be reliably measured using
UNC_CXLCM_TxC_PACK_BUF_INSERTS.MEM_DATA.
This works as expected and gives device statistics.Read bandwidth from the same CXL device, however, cannot be measured using the corresponding Rx event
UNC_CXLCM_RxC_PACK_BUF_INSERTS.MEM_DATA – it always shows zero, even under heavy read traffic.
Instead, on Sapphire Rapids (where nearMemoryMetricsAvailable() returns false), PCM falls back to CHA‑based events like
UNC_CHA_TOR_INSERTS.IA_MISS_DRD_CXL_ACC, which only provide socket‑level read bandwidth for CXL device.
From the Intel PCM source code (pcm-memory.cpp, cpucounters.h), I understand that on newer platforms like Granite Rapids or Sierra Forest (nearMemoryMetricsAvailable() == true), the UNC_CXLCM_RxC_PACK_BUF_INSERTS.MEM_DATA event does work and gives per‑CXL‑device read bandwidth. So the difference is clearly platform‑dependent.
My main question is: On 4th Generation Intel Xeon (Sapphire Rapids), why is it impossible to obtain CXL read bandwidth via the event UNC_CXLCM_RxC_PACK_BUF_INSERTS.MEM_DATA?
What is the architectural or microarchitectural reason that prevents UNC_CXLCM_RxC_PACK_BUF_INSERTS.MEM_DATA from counting reads on these “traditional” platforms?
Thank you in advance for any insights!
Best regards,
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Hi countingStars,
Greetings for the day!
Thank you for contacting Intel Support. We acknowledge receipt of your concern and would like to assure you that assisting you is our top priority.
We kindly request you to share the complete product details and system information. Providing this information will help us diagnose and resolve the issue more efficiently.
We look forward to your response.
Best regards,
Poojitha N
Intel Customer Support Technician
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