tuning 0xc8b register by wrmsr command

[sc3289]

Hi.

I am currently working with an Intel Xeon Gold 6354 processor.

(ice lake)

I'm attempting to increase the DDIO portion of the L3 cache through MSR settings.

Specifically, I have been using the wrmsr 0xc8b command, aiming to allocate a larger portion of the LLC to DDIO.

ex) wrmsr 0xc8b 0xF00

ex) wrmsr 0xc8b 0xFC0

However, upon testing with iperf3 to generate network flows and measuring L3 cache miss rates via perf, it seems that changing the MSR settings with wrmsr 0xc8b is not increasing the IIO_LLC_WAYS allocation as expected.

Could you provide guidance on whether adjusting 0xc8b for this model is indeed effective for increasing DDIO allocation within the LLC?

If there is an alternative method or a specific MSR configuration applicable to the Intel Xeon Gold 6354, I would appreciate any information or insights on how to properly increase the DDIO portion of the LLC cache.

Thank you very much for your assistance.

[sc3289]

Dear Akshaya,

Greetings!

Thank you for your confirmation regarding DDIO portions being managed independently for each CoS.

Currently, I am in the process of verifying whether the DDIO portion can indeed be increased using the pqos command. To ensure I have a clear understanding, I would like to ask two follow-up questions:

1. Previously, I attempted to increase the DDIO portion by modifying the value of the 0xc8b register using the wrmsr command. However, your explanation indicated that in Ice Lake, instead of using the 0xc8b register, the allocation of LLC ways for CoS via the pqos command is the method to adjust the DDIO portion. Have I understood this correctly?

2. Your response mentioned, "it is important to note that Intel DDIO is typically configured to use a subset of the L3 cache, and the degree of control over this allocation can be limited by the processor's firmware and BIOS settings." Based on this, it seems that the ability to adjust the DDIO portion via the pqos command could be restricted or even entirely unavailable due to firmware or BIOS limitations. Does this interpretation align with your explanation?

Thank you in advance for your assistance and clarification.

Best regards,
sc3289

[Fikri_Intel]

Hi sc3289,

Thank you for your response.

Based on your queries, we can confirm that your statements are correct.

Let us know if you have further concerns.

Regards,

Fikri

[pujeeth]

Hi sc3289,

Greetings!

Could you please confirm if the issue has been resolved? If so, are we good to proceed with closing this case

Regards,

Pujeeth

Intel Customer Support Technician

intel.com/vroc

[sc3289]

Dear Pujeeth,

Greetings!

I regret to inform you that I was ultimately unable to modify the DDIO portion using the methods you suggested. I attempted both the wrmsr and pqos commands but was unsuccessful in changing the DDIO portion.

Through further investigation, I discovered that, at least on the server I am using, the LLC ways allocated to CoS are distinct from the DDIO portion, contrary to what was described in your response.

It seems there is no viable way to modify the DDIO portion in my current setup, and therefore, I have no further questions on this matter.

If no alternative methods are available, you may consider closing this case. I truly appreciate the effort and support you have provided thus far.

Thank you again for your assistance.

Best regards,
sc3289

[Fikri_Intel]

Hi sc3289,

Thank you for getting back to us and for your understanding.

After carefully reviewing the situation, we regret to inform you that there are no alternate methods available to address this matter at this time. Considering this, we will proceed to archive this thread.

If you need any additional information, please submit a new question as this thread will no longer be monitored.

Regards

Fikri