Invitation to evaluate Intel® MKL Sparse Matrix Vector Multiply Format Prototype Package for Intel® Xeon Phi™ coprocessors
We are seeking interested parties to evaluate Intel® MKL SpMV Format Prototype Package for Intel® Xeon Phi™ coprocessors. Sparse Matrix Vector Multiply (SpMV) is an important operation in many scientific applications, and its performance can be a critical part of overall application performance. On Intel® Xeon Phi™ coprocessors, Intel® MKL 11.0 and later provide highly-tuned SpMV kernels for the compressed sparse row (CSR) sparse matrix storage format. But the existing standard (NIST*) sparse BLAS interface has limitations that prevent us from realizing further performance improvements, especially for matrices with non-uniform sparsity structures. The Intel® MKL SpMV Format Prototype Package tries to address these limitations by introducing a new interface that supports a staged approach: First, the input matrix structure is analyzed and an appropriate computational kernel and workload balancing algorithm are chosen. Then, repeated SpMV calls can be made for matrices of the same structure. As long as the total time required for the analysis stage and multiple SpMV calls is less than that of multiple individual generic SpMV calls, we will see improved overall performance.