How are L2 Cache TLB managed?

[JGio]

Hello,

I would like to know how L2 Cache TLB entries are managed during use. I have two specific questions.

1) Are L2 cache TLB entries evicted when a page fault occurs from the used entry? For example, the L2 cache TLB entry has N/X bit set but the access is an instruction fetch.

2) If the L2 cache TLB doesn't have a TLB entry for a virtual address, but the L1 cache TLB does have an entry for the virtual address, does the L1 cache TLB entry get promoted or copied to the L2 cache on access/use?

My questions are very relevant for L2 unified caches.

Thanks,

Jason

[Allan_J_Intel1]

Thanks for joining the Processor community.

I am currently researching on this issue. I would like to know if there is any specific processor family.

Allan.

[JGio]

Should different processor families have different behaviors for managing unified L2 cache TLB entries? Can you comment one whether different processor families have different L2 cache TLB management?

I am really only concerned with any processors with a unified L2 cache. I am led to believe that this includes all processors after 2008 which have the nehalem architecture or newer.

Thanks,

Jason

[Allan_J_Intel1]

Thanks for the update. I will update this thread when I have additional information.

Allan.

[Allan_J_Intel1]

Thanks for your patience.

I got response from engineering team: We strongly recommend contacting our developer forum, we regret to inform that at this level, this type of information is not available through this channel.

https://software.intel.com/en-us/forum Forums

Thanks

Allan.