NiosII processor cannot boot from EPCS16 with using the Serial Flash Controller IP core in Cyclone 10 LP design system

[NLei0]

Hi,

I has been using EPCS Flash controller core to access my Winbond W25Q16 Serial Flash in the Cyclone IV design system. Now I am updating my device to Cyclone 10 LP. The EPCS Flash controller core doesn't support by Cyclone 10 LP, so I use the Serial Flash Controller IP core to replace it and use Memcpy-based boot copier Method to boot my NiosII Processor ( design reference: Nios II Processor Application Copied from EPCQ Flash to RAM Using Boot Copier https://www.intel.com/content/www/us/en/programmable/documentation/iga1446487888057.html#fwl1479912385825).

When I load the .jic file to the flash, the Cyclone 10 has been configured but the processor never boot. I try to debug the software and I am stuck at "Error: Connected system ID hash not found on target at expected base address". If I exclude Serial Flash Controller IP core from my Qsys and not access the serial flash from code, everything works fine.

Does this Serial Flash Controller IP core support Cyclone 10 LP to access EPCS/Winbond Serial Flash?

Any help will be appreciated. Thanks in advance. BTW my environment is Quartus Prime Standard.

[AnandRaj_S_Intel]

Hi Lei,

Yes, We have to use Serial Flash Controller IP core for Cyclone 10 LP.  

Try to compare your design with the reference design.

https://fpgacloud.intel.com/devstore/platform/17.0.0/Standard/boot-from-epcq-serial-flash-example/

https://synaptic-labs.s3.amazonaws.com/pub/2017-Designs/SynapticLabs-HBMC-Tutorial-004/SynapticLabs-HBMC-Tutorial004A-NiosII-HyperRam_Boot_EPCQ.pdf

Regards

Anand

[NLei0]

Hi Anand, Thank you very much for your information. After many debugging I found my problem is not caused by the Serial Flash controller and I am not be able to debug my Nios II software on my hardware(10CL025YE144I7G). To exam my hardware system I made a very simple Platform Designer system just including basic components(clk, Nios2, on-chip ram, jtag-uart and LED output) and set the reset vector and exception vector memory on the on-chip-ram. Then in the Quartus Prime I have PLL and reset logic to clock and reset the system. On NiosII Eclipes I just use the “ hello world” demo project. After I downloaded the .sof file to the FPGA, I tried to debug Hello world as a hardware and I got the error “Connected system ID hash not found on target at expected base address”. Screenshots of my bdf and error information, qsys file are attached for your reference. Please let me know if you need more information. Thanks you very much! Best regards, Na Sent from Mail<https://go.microsoft.com/fwlink/?LinkId=550986> for Windows 10

[AnandRaj_S_Intel]

Hi Na,

I can't access the files attached.

Attach it in forum directly.

Is you design working fine without debug?

“Connected system ID hash not found on target at expected base address”.

>>Go to Run As->Run Configuration -> makes Nios to ignore the system ID and timestamp, and check.

Regards

Anand

[NLei0]

Hi Anand, My problem is solved today. It turns out being the reset signal problem on the hardware. Thanks a lot for your quick response. Your time and support are greatly appreciated. Best regards, Na