- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello,
I found that integrated memory controller of Intel Xeon E5-2600 supports DDR4 ALERT_n signal for Parity error. Does it support ALERT_N for CRC error also?
I also found that some Intel processors have limited support of ALERT_n signal . Their datasheets say following:
"Alert_n: This signal is used at command training only. It is getting the Command and Address Parity error flag during training".
Does it mean that a memory controller would get the signal only during BIOS initialization and would ignore it after, even a DIMM module asserts the signal?
Thank you
Alex
Link Copied
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello, shalex:
Please let me review this information, as soon as I have an answer I will let you know.
Regards,
Amy.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello,
Do you have more information on my question?
Thank you
Alex
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
shalex, I apologize for the delay.
If the Xeon processor supports DDR4 then it supports Alert_n feature. However, if you would like to get more information on how this feature works the right place to ask questions would be https://software.intel.com/en-us/forum https://software.intel.com/en-us/forum.
Regards,
Amy.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello, /thread/102279 shalex:
I just wanted to confirm if the information provided above was helpful. Would it be ok if I close the thread?
If you have more questions please let me know.
Regards,
Amy.
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page