Xeon memory bandwidth

[TPtac]

Hi,

I'm trying to understand the maximum (theoretical) memory bandwidth of Xeon processors so that our applications can maximize their bandwidth. I thought I had it figured out, but now I have a processor where I don't understand how the maximum numbers make sense.

Here's an example I think I understand: Xeon E5-2630 v3 (Haswell-EP). The maximum memory bandwidth (according to ARK) is 59 GB/s. It has 4 memory channels and supports up to DDR4-1866 DIMMs. The peak transfer rate of a DDR4-1866 DIMM is 14933 MB/s, and 14933 * 4 = 59732 MB/s, so this adds up.

What I don't understand: Xeon E7-4830 v3 (Haswell-EX). The maximum memory bandwidth is 102 GB/s. But it also supports up to DDR4-1866 and has 4 memory channels! So how does it get 102 GB/s? One theory is that the E7-4830 v3 has two memory controllers. While cpu-world confirms this, it also says that each controller has 2 memory channels, so it still doesn't add up.

I'd appreciate any help from the experts over here. Is the number of memory controllers documented by Intel anywhere? I couldn't find it.

Thanks in advance!

[idata]

Hello tptacek,

Please let me review your inquiry, as soon as I have more information I will update the thread.

Regards,

Amy.

[idata]

/thread/109769 tptacek, I am still reviewing your case.

Thank you for your patience.

Regards,

Amy.

[idata]

The Xeon E7-4830 v3 has 4 memory buffers, each buffer has 2 channels = 8 channels / CPU. Thus, 14933 * 8 = ~120 (minus overheads); giving you an effective 102 GB/s advertised on ark.intel.com.

Best publicly available collateral that I have found was from Anandtech on an older Ivy Bridge, but the principle is the same...

http://www.anandtech.com/show/7757/quad-ivy-brigde-ex-60-cores-120-threads/3 Now with High Bandwidth Memory - The Intel Xeon E7 v2 Review: Quad Socket, Up to 60 Cores/120 Threads