Re: Altera_Avalon_SPI Cyclone II DSK

Altera_Forum · ‎03-01-2016

I have a NIOS II/s processor at 50 MHz that has an two SPI's which interfaces with TI's AIC23 on the Cyclone II DSK board. One (master) SPI programs the AIC23. Other (Slave) SPI does the data transfer. The AIC23 programs OK. The data transfer does not work correctly.

I have a loopback shift register. It works OK. This means the SS_N chip select I generate is working.

I have an SPI VHDL code I wrote. It works OK.

Anyone know why or has had similar problems with the Altera_Avalon_SPI in slave mode has problems? I have tried everything.

Thanks

Altera_Forum · ‎03-01-2016

I have found something. I am able to get the audio working like it should but I don't know if the problem is with the Altera_Avalon_SPI or a software issue. More test are needed.

Altera_Forum · ‎03-03-2016

I believe the Altera_Avalon_SPI is "slave" mode has problems. If not, I want to see the code/QSYS for a simple system to read/write 10 msec of data at 44.1 KHz sample rate from the AIC23 on a Cyclone 2 DSK board.