Nios® V/II Embedded Design Suite (EDS)
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Altera Monitor Program- Nios 2 processor

Altera_Forum
Honored Contributor II
‎08-29-2011 09:45 AM
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When I try to load the program to DE2 board I get the following error:- There are no Nios II CPUs with debug modules available which match the values 

specified. Please check that your PLD is correctly configured, downloading a 

new SOF file if necessary. I am new to FPGA. Please help me
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Altera_Forum
Honored Contributor II
‎08-30-2011 07:38 AM
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Did you configure the FPGA first? Ensure that both your software and the .sof FPGA image that you load are based on the same design.

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Altera_Forum
Honored Contributor II
‎08-30-2011 07:54 AM
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yes sir i have done everything you mention and my software and .sof image are based on the same design.

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