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Altera_Forum
Honored Contributor I
1,728 Views

Boot two cores in cyclone V with two different programs or OS?

Hello everyone! I have deal with soc for several month, and i almost scanned all the topics in this forum. 

We mostly talk about the core# 0. so I am confused that why no topic mentioned about how to use the core# 1? 

We all know that Linux OS will manage both cores in SMP mode. But in a baremental project, how we take full use of the second core? 

 

I have two questions: 

:evil:1: baremental(core# 0) + baremental(core# 1) mode 

ACHIEVED: I have achieved running two cores using JTAG line to load programs, and it works will! 

QUESTION: How we boot the both cores automatically? I have tried using core#0 to load program of core#1 to a specific ddr3 location, release core#1 from reset, but i failed. I can't read the data successfully from nand flash using HWLIB divers. 

:evil:2: Linux(core# 0) + baremental(core# 1) mode 

ACHIEVED : I can running linux on core# 0, meanwhile ,I can load core#1 's program using JTAG line, it works well! 

QUESTION: How can linux load core# 1's program from file system. I have no time to do this experiment! 

 

I will be thankful for any advice for me. help.....
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9 Replies
Altera_Forum
Honored Contributor I
78 Views

To run different programs on the cores, there is no need to have core# 0 to load the program for core# 1. 

The memory is shared between both cores, and if the cache is not set for non-shared, both processors see the same memory. 

Upon reset, core# 0 is allowed to run and core# 1 remains under reset. 

There is a short sequence to perform with core# 0 to inform core# 1 where to start executing and to release it from reset. 

We have a version of our SMP RTOS available as freeware. 

There is a demo in that free package showing how to do bare-metal using both cores. 

You can download it from:  

www.code-time.com 

 

Regards
Altera_Forum
Honored Contributor I
78 Views

Hello ericv! 

I am grateful for you reply! You open a new window for me, and it is totally new scene outside the window! 

I have downloaded this freeware package from code-time. I read the code roughly! I find some point: 

1: Is this program open source? Some vital functions such as "OSstart()、OSintOn()、TSKcreate("App Core 1", 0, 8192, &App_1, 1)"..... 

I can only find their declaration in head file "uAbassi.h", but their source has been compiled into a lib file. 

 

2: I know such a bare-metal project is just an operating system. It takes a lot effort to finish such a project! 

I am very interested about how function "TSKcreate()" executed in core# 0 makes core# 1 execute "app_1" ?  

When we release core# 1 from reset, it will jump to a specific address and run, the question is how do we know where to jump?  

How core# 1 finish initialization? I remember there is a file called "start.s" in UCOS ii to set up core# 1. 

 

I must have a lot of knowledge to learn! Can you suggest some books, blogs, PDF documents or else for me. I am thirsty for this! 

Waiting for you reply! best wishes!
Altera_Forum
Honored Contributor I
78 Views

You can find all the information about TSKcreate() and all other RTOS services in the user manual. 

The manual is downloadable from the website. 

The package contains strip down version of our SMP multi-core core, and the bare-metal example is simply an application running only 2 tasks. 

- 2 cores with 2 tasks means each core run one of the 2 tasks, different from the other core. 

For books, blogs, etc: 

a quick search on "RTOS tutorial" would be a good starting point.
Altera_Forum
Honored Contributor I
78 Views

Hi zhuyue0414,  

I am using Cyclone V SoC. I wanted to use both cores(in SMP mode) in bare metal applications. 

How did you achieved running two cores using JTAG? 

How to select the core number from DS-5? 

help me in this regard. 

 

-- 

Selvakumar
Altera_Forum
Honored Contributor I
78 Views

In the debug configuration (connection tab), select: 

Altera 

Cyclone V SoC (Dual Core) 

Bare Metal Debug 

Debug Cortex-A9x2 SMP 

 

Then you have to run an appropriate initialization script to set-up the cores / debugger & load the program. 

 

Regards
Altera_Forum
Honored Contributor I
78 Views

Hi, 

Can you suggest what changes has to be made in the initialization script to set-up the cores / debugger & load the program. 

Also can you provide basic initialization script/Project to proceed further. 

It will be of great helpful. 

Thank you.
Altera_Forum
Honored Contributor I
78 Views

Download any of our SMP freeware for the Cyclone V device from 

code-time.com/smp_free.html 

 

Each DS5 project has a DS5 script named debug-nonhosted.ds (they are at the tip level inside the projecst. 

All you need to change in them is the name of binary file loaded and that's near the end of the script 

The package also include the SPL / U-boot for the supported boards. 

Each command in the scripts are commented; that should allow you to understand step by step what needs to be done. 

 

Regards
Altera_Forum
Honored Contributor I
78 Views

 

--- Quote Start ---  

 

 

I have two questions: 

:evil:1: baremental(core# 0) + baremental(core# 1) mode 

ACHIEVED: I have achieved running two cores using JTAG line to load programs, and it works will! 

 

--- Quote End ---  

 

Could you please explain how you did it? I can't find any info about that. Thanks!
AJama4
Beginner
78 Views

Can you post a short description describing briefly the steps you did to boot two cores with different programs. I bet it will be really helpful for the novice users!

 

Thanks!

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