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How do I boot HPS of Cyclone V SoC on AMP

Altera_Forum
Honored Contributor II
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Now I'm trying to boot HPS of Cyclone V SoC on AMP. 

I would like to operate different bare metal programs on each core. 

 

Has anybody tried the same thing? 

I would really appreciate it if somebody can provide any tips regarding it. 

 

I have no ideas for it, but I have some guesses to do that, # 1. Do I need to boot CPU#0 at first normally, then do something on CPU#0 in order to launch CPU#1?# 2. Do I need to edit the FPGA configuration to launch both cores with Qsys?# 3. Do I need to make a "special" preloader for it? 

 

Now I'm using DS-5 (Altera Edition) bundled with my Cyclone V SoC development kit. 

(It likely supports booting dual core on "SMP"...)  

 

Thanks,
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Altera_Forum
Honored Contributor II
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Considering a final product, to get an AMP system up and running can be done like this: 

1 - A single image is loaded in memory, core# 0 starts and core# 0 informs core# 1 where to start executing in this image. 

That requires you to merge the 2 app in a single image. 

2 - Load an image, then the core# 0 loads another image and inform core# 1 where to start (using the loaded image). 

 

In DS-5, as far as I know, there are not GUI set-ups to download 2 images. 

You have to do it with a script. 

In the Debugger tag, add the script in the box: 

"Run debug initialization debugger script" 

The script syntax is quite simple and in it you can perform 2 sequential loads if you are using 2 images. 

 

I am not a fan of AMP if you ever think about using an RTOS on 2 cores. 

For bare-metal, then we can simplify your life. Go to: 

code-time.com 

in the multi-core freeware section download uAbassi, (not mAbassi) for the Cyclone V. 

There's a working bare-metal demo in it. 

It should be easy to put your bare-metal 2 core application in that demo. 

Instead of dealing with 2 images, you'll only have to deal with one image and 2 entry functions (one function per core). 

And the debug script is included. 

 

Regards
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Altera_Forum
Honored Contributor II
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Hello ericv, 

 

Thank you so much for your great support. 

Now I'm considering how to realize the steps you showed me. It's likely your 2nd method is easier than the other? 

 

And in order to learn regarding the syntax of the script, I'm checking the .ds and .axf files in μAbassi sample project. 

Probably I will have some more questions, but I need long time to understand it. 

 

Thanks,
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Altera_Forum
Honored Contributor II
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Not only you'll get a single image using uAbassi, but it is also a single "application" or "executable". 

This is useful as the code running on the cores will quite likely exchange data/information. 

With 2 images, you have to reserve memory sections in the linker that are dedicated for the exchange. 

With uAbassi, you do that with global variables, the same as exchanging data between 2 functions... because the two apps are two functions. 

 

If you plan to use 2 images, then you have another option, as you are on a Cyclone V, which is to rely on U-boot. 

If you look in this doc 

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-v/cv_5400a.pdf 

The preloader would typically run and load U-boot. 

In U-boot, you can do a lot of things. 

Among them is to load files from Flash, SD/MMC, etc 

You can load your 2 executable through U-boot and then run the app for core# 0 (U-boot runs on core# 0), when running released core# 1 from reset. 

You put everything you want to do in a script that is auto-executed upon start-up. 

 

Regards
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Altera_Forum
Honored Contributor II
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Hello ericv, 

 

 

Thank you. 

I understood the advantage of the single image thanks to your explanation. 

 

I'm still referring uAbassi source codes, but I have no idea about how it release Core#1 and how it indicates to execute App_1 on Core#1. 

If I have a big misunderstanding, please let me know... 

 

 

And I also referred the document you introduced. This looks very nice to learn the outline of booting and configuration in my Cyclone V SoC. 

It says "The user software in CPU0 is responsible to release CPU1 from reset.", but unfortunately this document doesn't show how to do that. 

Is it better to refer Cortex-A9 MP core documents regarding U-boot or more subsequent booting processes? 

 

I appreciate for your continuous support! 

 

Thanks,
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ALTERA-INSUPPORT22
New Contributor I
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Assistance Needed: Trouble Running Bare-Metal Code on Cyclone 5 HPS


I am working on intel cyclone 5 hps I have two cores in a processor Core 0 core 1, I want two code to run on two different cores core 0 and core 1 in bare metal .


When I run in jtag mode it works, for jtag i first debug using core 0 where i take core 1 out of reset it, than debug core 1 usign jtag it work


BUT, When i want to run both core usign qspi it only run core 0 not core 1


Here is the step i followed

Firsly, loading preloader
quartus_hps -c 1 -o P preloader-mkpimage.bin

I make an image from bin file of core 0 and place it to qspi

mkimage -A arm -O u-boot -T standalone -C none -a 0x00060000 -e 0 -n "baremetal image" -d core0.bin core0.img

quartus_hps -c 1 -o P -a 0x00060000 core0.img

I make an image from bin file of core 1 and place it to qspi
mkimage -A arm -O u-boot -T standalone -C none -a 0x00100000 -e 0 -n "baremetal image" -d core1.bin core1.img
quartus_hps -c 1 -o P -a 0x00100000 core1.bin


When i restart board only that code work which is in core 0, core 1 code not executing

I am setting cpu1startaddress 100000 apart from that in the code of core 0 also i am using alt_qspi function to to place bin file data in ddr, 

I want to run in smp mode so I also set required aux_control_register smp and fw bit as stated in tech ref manual  


alt_qspi_read((uint32_t *)BL_START/*ddr3 address*/, 0x100000/*qspi address*/, 0x40000);


In linker/scat file core 0 entry point is 0x60000 and

linker/scat file core 1 entry point is 0x100000

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Altera_Forum
Honored Contributor II
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The information you are looking for about the boot of the 2nd core in in the System Manager section in the Cyclone V Handbook. 

Regards
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Altera_Forum
Honored Contributor II
1,569 Views

Hello ericv, 

 

Thank you so much for your additional information. 

I found it in "Cyclone V Hard Processor System Technical Reference Manual"! 

 

My initial question now becomes clear, although probably I will have a few more problems to achieve the original stuff I want to do, 

 

Everything is thanks to you! 

I really appreciate your cooperation. 

 

Thanks,
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