Dev board, Stratix II Edition, how to boot?

[Altera_Forum]

Hi there, I am a newbie to this Altera stuff! Hope anyone can help. 

 I have successfully booted uClinux on a Stratix edition dev board using the following steps. 1. Build and upload kernel to flash 2. Build and upload filesystem to flash 3. Load .sof file to FPGA 4. Use nios2-terminal to connect and boot kernel. It seems the kernel does not boot until you connect.  I have tried the same steps on a Stratix II edition board with no success. I get to step 4, but then it seems the JTAG service is not available. I get the following message: "[SOPC Builder]$ nios2-terminal.exe nios2-terminal: Unable to connect to local JTAG server. Please check that nios2-terminal: Quartus II is correctly installed on your machine and use the nios2-terminal: `jtagconfig` utility to diagnose further."  jtagconfig produces: "[SOPC Builder]$ jtagconfig.exe 1) ByteBlasterMV [LPT1]  020930DD EP2S60"  The 7-segment display is showing "88" which usually means the .sof loading was successful.  I get the same whether I use the Byte Blaster or the USB Blaster.  Anyone succeeded in booting the Stratix II?  Why is step 4 required? How do you get it to boot with out connecting via the JTAG port?  Thanks

[Altera_Forum]

Hi, sorry must've missed this post when I was scanning the last time around... the 4th step you're referring to is required because: 

 (1) The kernel console messages are (by default) sent to the JTAG uart. (2) There's some sort of buffering issue with the JTAG UART driver that blocks the kernel from continuing until the buffer is cleared (3) Until nios2-terminal is started, the output buffer on the JTAG UART can't clear so the kernel blocks.  As for the Stratix II board, we don't have one in house so we haven't been able to test on it I'm afraid.