Hello,1) Is the GHRD ghrd_5astfd5k3 compatible with the ArriaV SoC Development Board? 2) According to the GHRD ghrd_5astfd5k3, some of GPIOs are selected instead of the EMAC1 ports in the HPS Peripheral Mux (e.g. GPIO17 instead of EMAC1.TXD2, GPIO18 instead of EMAC1.TXD2, etc - please see below the shortcut). So, how the EMAC1 can work if some of its ports are disabled (GPIOs are used instead of them)? http://www.alteraforum.com/forum/attachment.php?attachmentid=11601&stc=1 Thank you!
Looks like this 5astfd5k3 that you openned is 14.0 GHRD for Arria V already..You are right, this looks not going tp work..how ever i think most of the emac design example are in cyclone v which is already enabled those pins for utilization, i open up for cyclone one all with emac pin selection. did you tried open some of the design example say for cyclone V?