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Altera_Forum
Honored Contributor I
932 Views

How to provide different clock for PHY Device

My board DE2-115 

My PHY Device:88E1111 

 

My project is about simple socket server.Now I can send words or command via Telnet or Ping, when I use a router(100Mbps). 

But, when I directly connect the board and PC with a cross-over cable , I failed. 

Then when I fix my pc for 100Mbps and connect the board and PC with a cross-over cable, I succeed. 

So if I want to use 1000Mbps, what should I do ? 

I know I need to provide different clock to Marvell 88E1111 PHY Device for different speed. Such as 2.5MHz for 10mbps/ 25MHz for 100mbps /125MHz for 1000mbps. 

 

Who can tell me how to change the clock and where to change the clock,provided for phy device. 

 

It is the first time for me to post a thread, I hope that somebody could help me to solve this problem.
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27 Replies
Altera_Forum
Honored Contributor I
88 Views

Use example projects and search for file mii_gmii_mux.vhd. Or You can write Your own clock mux.

Altera_Forum
Honored Contributor I
88 Views

 

--- Quote Start ---  

Use example projects and search for file mii_gmii_mux.vhd. Or You can write Your own clock mux. 

--- Quote End ---  

 

Dear Socrates, thanks for your reply. 

I find the file GMII_MII_MUX.v 

But I still don't know how to change these codes.They are as follows: 

******************************************************** 

 

module GMII_MII_MUX ( 

//--- PHY Interface 

reset_rx_clk_n, 

phy_rx_clk, 

phy_rx_col, 

phy_rx_crs, 

phy_rx_d, 

phy_rx_dv, 

phy_rx_err, 

reset_tx_clk_n, 

tx_clk_ref125, // 125MHz TX local reference clock 

tx_clk_phy125, // 125MHz TX clock for GMII 

tx_clk_mac, // TX clock to use by the MAC 

tx_clk, // 25MHz/2.5MHz TX clock from PHY, 

phy_gtx_clk, // TX clock to PHY 

phy_tx_d, 

phy_tx_en, 

phy_tx_err, 

phy_mdio, 

//--- Local MII Interface 

m_rx_col, 

m_rx_crs, 

m_rx_d, 

m_rx_dv, 

m_rx_err, 

m_tx_d, 

m_tx_en, 

m_tx_err, 

//--- Local GMII Interface 

gm_rx_d, 

gm_rx_dv, 

gm_rx_err, 

gm_tx_d, 

gm_tx_en, 

gm_tx_err, 

//---  

eth_mode, //--- Mode select, from MAC configuration, 1 : Gigabit, 0 : 10/100 

ena_10, 

mdio_in, 

mdio_oen, 

mdio_out 

); 

//========================================================= 

// PARAMETER declarations 

//========================================================= 

//========================================================= 

// PORT declarations 

//========================================================= 

//--- PHY Interface 

input reset_rx_clk_n; 

input phy_rx_clk; 

input phy_rx_col; 

input phy_rx_crs; 

input [7:0] phy_rx_d; 

input phy_rx_dv; 

input phy_rx_err; 

input reset_tx_clk_n; 

input tx_clk_ref125; 

input tx_clk_phy125; 

output tx_clk_mac; 

input tx_clk; 

output phy_gtx_clk; 

output [7:0] phy_tx_d; 

output phy_tx_en; 

output phy_tx_err; 

inout phy_mdio; 

//--- Local MII Interface 

output m_rx_col; 

output m_rx_crs; 

output [3:0] m_rx_d; 

output m_rx_dv; 

output m_rx_err; 

input [3:0] m_tx_d; 

input m_tx_en; 

input m_tx_err; 

//--- Local GMII Interface 

output [7:0] gm_rx_d; 

output gm_rx_dv; 

output gm_rx_err; 

input [7:0] gm_tx_d; 

input gm_tx_en; 

input gm_tx_err; 

//--- 

input eth_mode; 

input ena_10; 

output mdio_in; 

input mdio_oen; 

input mdio_out; 

//========================================================= 

// REG/WIRE declarations 

//========================================================= 

wire tx_clk_int; 

reg mode_reg1; 

reg mode_reg2; 

reg [7:0] gm_rx_d_r; 

reg gm_rx_dv_r; 

reg gm_rx_err_r; 

reg gtx_clk; 

//========================================================= 

// Structural coding 

//========================================================= 

// mdio tristate 

assign mdio_in = phy_mdio; 

assign phy_mdio = mdio_oen ? 1'bz : mdio_out; 

// PHY RX input 

always @(negedge reset_rx_clk_n or posedge phy_rx_clk) 

begin 

if (reset_rx_clk_n == 1'b0) begin 

gm_rx_d_r <= 8'b00000000; 

gm_rx_dv_r <= 1'b0; 

gm_rx_err_r <= 1'b0; 

end 

else begin 

gm_rx_d_r <= phy_rx_d; 

gm_rx_dv_r <= phy_rx_dv; 

gm_rx_err_r <= phy_rx_err; 

end 

end 

// MII RX local interface 

assign m_rx_col = phy_rx_col; 

assign m_rx_crs = phy_rx_crs; 

assign m_rx_d = gm_rx_d_r[3:0]; 

assign m_rx_dv = gm_rx_dv_r; 

assign m_rx_err = gm_rx_err_r; 

// MII RX local interface 

assign gm_rx_d = gm_rx_d_r[7:0]; 

assign gm_rx_dv = gm_rx_dv_r; 

assign gm_rx_err = gm_rx_err_r; 

 

// TX clock MUX 

always @(negedge reset_tx_clk_n or posedge tx_clk_ref125) 

begin 

if (reset_tx_clk_n == 1'b0) begin 

mode_reg1 <= 1'b0; 

mode_reg2 <= 1'b0; 

end 

else begin 

mode_reg1 <= eth_mode; 

mode_reg2 <= mode_reg1; 

end 

end 

assign tx_clk_int = mode_reg2 ? tx_clk_ref125 : tx_clk; 

assign tx_clk_mac = tx_clk_int; 

assign phy_tx_d = mode_reg2 ? gm_tx_d : {4'b0000,m_tx_d[3:0]}; 

assign phy_tx_en = mode_reg2 ? gm_tx_en : m_tx_en; 

assign phy_tx_err = mode_reg2 ? gm_tx_err : m_tx_err; 

 

// GXT_CLk driver 

ddr_o gen_gxt_clk 

.datain_h(1'b1), 

.datain_l(1'b0), 

.outclock(tx_clk_phy125), 

.dataout(phy_gtx_clk) 

); 

endmodule  

******************************************************** 

Can you tell me what should I do to get 125MHz for PHY Device and then enable the 1000Mbps? 

 

Have a good day,Socrates.
Altera_Forum
Honored Contributor I
88 Views

Just look at the top level file in the example project and do the same in yours.

Altera_Forum
Honored Contributor I
88 Views

generate 125MHz clock using PLL.

Altera_Forum
Honored Contributor I
88 Views

 

--- Quote Start ---  

generate 125MHz clock using PLL. 

--- Quote End ---  

 

Can I get 125MHz by changing GMII_MII_MUX.v?
Altera_Forum
Honored Contributor I
88 Views

DO NOT TOUCH CONTENTS OF THAT FILE. Usually, it is already read-only. 

 

You have to generate 125MHz Yourself and supply that clock to the mii/gmii mux core. It's simple to read comments and undestand how it work. Do that instead of asking in forum. Ask here things that You can't get running, but not things, that You don't understand.
Altera_Forum
Honored Contributor I
88 Views

 

--- Quote Start ---  

Just look at the top level file in the example project and do the same in yours. 

--- Quote End ---  

 

What I used is just the example project, but it didn't work when fix my pc for 1000Mbps. 

So i want to change the colck, provided for PHY Device, from 25Mhz to 125Mhz. 

However, I don't know how to change it in GMII_MII_MUX.v.
Altera_Forum
Honored Contributor I
88 Views

The clock ,provided for PHY Device and determine the transfer speed&#65292;is GTX_CLK or something else?

Altera_Forum
Honored Contributor I
88 Views

 

--- Quote Start ---  

DO NOT TOUCH CONTENTS OF THAT FILE. Usually, it is already read-only. 

 

You have to generate 125MHz Yourself and supply that clock to the mii/gmii mux core. It's simple to read comments and undestand how it work. Do that instead of asking in forum. Ask here things that You can't get running, but not things, that You don't understand. 

--- Quote End ---  

 

In Ethernet RX PLL, the inclk--enet_rx_clk is 125MHz, the outclk--c2(enet_tx_clk_phy) is also 125MHz. And enet_tx_clk_phy is the outclock of ddr_o phy_ckgen .As follows: 

*************************************** 

ddr_o phy_ckgen 

.datain_h(1'b1), 

.datain_l(1'b0), 

.outclock(enet_tx_clk_phy), 

.dataout(enet_gtx_clk) 

); 

// Ethernet RX PLL 

enet_rx_clk_pll enet_rx_clk_pll 

.inclk0(enet_rx_clk), 

.c0(enet_rx_clk_270deg), 

.c1(enet_tx_clk_mac), 

.c2(enet_tx_clk_phy) 

); 

**************************************** 

I was really confused why 1000Mbps isn't work.
Altera_Forum
Honored Contributor I
88 Views

 

--- Quote Start ---  

DO NOT TOUCH CONTENTS OF THAT FILE. Usually, it is already read-only. 

 

You have to generate 125MHz Yourself and supply that clock to the mii/gmii mux core. It's simple to read comments and undestand how it work. Do that instead of asking in forum. Ask here things that You can't get running, but not things, that You don't understand. 

--- Quote End ---  

 

Hi Socrates,I have changed the output clock of PLL to 125Mhz, provided for MAC. But 1000Mbps is still failed. 

When you do something about ethernet, what did you do to enable 10Mbps and 100Mbps and 1000Mbps. You switch them by changing what? 

Hope for your reply.
Altera_Forum
Honored Contributor I
88 Views

The PHY provides that. Download and examine examples from Altera.

Altera_Forum
Honored Contributor I
88 Views

My project is just provided by Altera. 

My SOPC is WEB_SERVER(rgmii) provided by CD of DE2-115. 

MY software is simple_socket_server(RGMII) 

I need to change something in SOPCBuilder or top level file? The datasheet of 88E1111 show me that the frequency, provided for PHY, is changed automatically.  

When it is 1000Mbps, we get 125Mhz. 

When it is 100Mbps, we get 25Mhz.
Altera_Forum
Honored Contributor I
88 Views

That's true, but afaik You need GMII, not RGMII?

Altera_Forum
Honored Contributor I
88 Views

Shoule I use the WebServer(GMII)? 

I sorry that I do not understand what you mean.
Altera_Forum
Honored Contributor I
88 Views

Oh, just checked, that You use DE115. Then it's RGMII there.

Altera_Forum
Honored Contributor I
88 Views

Is there any possiblity that My pc does not support 1000Mbps?

Altera_Forum
Honored Contributor I
88 Views

It depends, check the motherboard or Your ethernet card specs.

Altera_Forum
Honored Contributor I
88 Views

When I conect my board and PC, the ENET0 LED1000 is bright. Does that mean my PC support 1000Mbps

Altera_Forum
Honored Contributor I
88 Views

I'd say yes, the board PHY recognize the 1Gbit link.

Altera_Forum
Honored Contributor I
25 Views

:cry::cry::cry:Then what can I do now to use 1000Mbps full duplex to transfer data?

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