Hi Intel Community,
I have a strange error with MDIO interface on the NIOS II.
I'm using it to communicate with an external PHY.
I got an generated altera_eth_mdio.v file from a colleague where everything works fine.
My code can perfectly read and write any registers from the external PHY when I'm using his generated NIOS-HDL files.
When I generate new HDL files in the Platform Designer I get a different altera_eth_mdio.v file. All other files stay the same.
With this file I can't access any registers on the external PHY over the MDIO interface.
The .qsys file is the same in both designs.
Could you tell me why the Platform Designer generates a different altera_eth_mdio.v file?
Actually the configuration of the MDIO is very easy and I have absolutly no idea what is going wrong.
My workaround is to replace the altera_eth_mdio.v with the good one after generating HDL files.
But that's not a good solution
I appended my .qsys file and both generated altera_eth_mdio.v files.
Thanks a lot for your help.
Ok, found it.
The TLK10232 we use in this project requires a longer MDIO preamble than the nios generates. So my colleague manually changed the file. And replaced it after generating new NIOS files. I didn't expect that...
We use Quartus Version18.1. Maybe in a newer Version this problem is fixed. If not it's maybe a good idea to make the preamble length configurable.
Have a nice day.