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Altera_Forum
Honored Contributor I
1,293 Views

NIOS simulation in Modelsim

Hi! 

 

My boss asked me to put together a NIOS system and simulate it successfully in Modelsim, and then show him how to do it. I was able to get the "Hello World" example to work (only when the project was built in Qsys, not SOPC builder for some reason), so I thought I would try something more complicated. 

 

My system is quite simple, 2 on chip memory, NIOS II, and a JTAG UART. I started a blank project from a template in the Eclipse SBT. The only thing I added to the blank project is a simple main function that loops through a couple memory addresses and does some reads and writes. The read/write to the memory is done with the IOWR/RD_32DIRECT functions supplied in the template. 

 

Problem is, the simulation doesn't do anything. I've let it run for really long periods, I've tried changing the code, BSP settings, everything I can think of. The waveforms in the test bench just load some instructions, do some datamem access, and repeat. The process just repeats with the same instructions and same data accesses over and over again every so often. The addresses of the data r/w look like it is probably heap/stack access. It seems to me that this activity is the HAL working and has nothing to do with my code. 

 

So why does my code not run? I can't see any difference between my settings and the simple "Hello World" example. I'm not trying to do anything to complicated. I even tried to run the Altera "Mem Test" example which also did not work. There must be something I'm missing but I don't know what it is. 

 

Any thoughts would be appreciated. Thank you!
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7 Replies
Altera_Forum
Honored Contributor I
70 Views

As fair as i know you can't simulate your system running on modelsim? You should use signal tap for that.

Altera_Forum
Honored Contributor I
70 Views

Well that would be unfortunate if I was set onto an impossible task. If the system running can't be simulated then why does the "Hello World" example work, and what is the difference?  

 

Can SignalTap be used to simulate? I've never heard that before, but then I have never used Signal Tap. I thought it is a logic analyzer, and I don't really interact with my designs once they are loaded to the chip. The test engineers deal with that. If SignalTap can do what you say, I'd really be interested in learning how to do it. Thanks for the quick reply!
Altera_Forum
Honored Contributor I
70 Views

here is mywork. 

http://www.akiron.com/fpga/baseprojectinverilog.zip 

 

chapter 4 and 5 has how to use signaltapII quickly. 

 

I think you can simulate niosII. 

[run]-[run as]->[NiosII model sim] 

(I think you have done it havn't you?) 

 

see you.
Altera_Forum
Honored Contributor I
70 Views

Simulation will take a while if you don't turn on the simulation support in your BSP. When this is enabled things like flushing the cache and other optimizations will not happen. Also don't forget to turn this option off when you want to run your software in hardware as these shortcuts should not be present when run in real hardware. 

 

What you are attempting should be possible.
Altera_Forum
Honored Contributor I
70 Views

Got it to work. Turned on the small C library and changed the NIOS so that it didn't have a cache. This made it easier to track each instruction in modelsim. Disabling the full C library made the sim run faster. Evidently the processor takes quite a while in simulation to boot up and load the necessary data, so changing settings to speed up this process works better. For simulation purposes on larger designs in the future I think that I'll have to simulate it overnight and optimizing the sim so that it won't take forever.

Altera_Forum
Honored Contributor I
70 Views

Also if you are running code from DDR(I/II/III) SDRAM there is around 250us worth of calibration time that gets simulated by default. You can disable this in the DDR(I/II/III) SDRAM controllers to speed things up. 

 

If you turn on the BSP simulation optimization you'll probably find having the cache enabled will be faster than disabling the cache and not using the BSP simulation optimization.
Altera_Forum
Honored Contributor I
70 Views

 

--- Quote Start ---  

Got it to work. Turned on the small C library and changed the NIOS so that it didn't have a cache. This made it easier to track each instruction in modelsim. Disabling the full C library made the sim run faster. Evidently the processor takes quite a while in simulation to boot up and load the necessary data, so changing settings to speed up this process works better. For simulation purposes on larger designs in the future I think that I'll have to simulate it overnight and optimizing the sim so that it won't take forever. 

--- Quote End ---  

 

can you please tell me how do you keep track of nios instructions execution in modelsim? 

and how to simulate our design when there is one custom component inside the qsys system? 

I appreciate if you attach any tutorial or picture of your qsys system. 

thanks