Hi,I'm trying to interface a NIOS2 with a self-designed VHDL module, a simple one. Until now I was using a 32 bit PIO for transferring data from the VHDL to the NIOS2, but I would like to increase the words size from 32 bits to 64 bits. As far as I read, PIOs deal up to 32 bit words. What I'm thinking is to split the word in two parts and then use 2 PIOS, but this is a kind of a silly solution because it will increase significantly the time to read the 64 bit-word from the VHDL module and this is a high-throughput process. Is there anyway to overcome this problem? Any suggestions? Shall I consider using an Avalon buffer? I would like to avoid that because it sounds complicated and the design is really simple... Thank you very much in advance, XB :rolleyes:
You are right, the PIOs are limited to 32 bits. I'm not sure I understand how using 2 PIOs will increase significantly the time. You will just perform two 32-bit operations instead of one.If you have a high thoughput you could consider using a DMA. The SGDMA or the modular SGDMA available on this forum can accept data from an Avalon Stream interface which is really easy to implement. AFAIK those DMAs can process 64-bit words.
Whatever you do the nios cpu can only load one 32bit word into a register in one instruction. A read from an Avalon slave will usually take 3 clocks (will be longer if any avalon bridges are needed, or if the slave stretches the cycle).What you might want to do is add an Avalon slave interface to your logic block - then you can use the low address bits to select the data to read/write.
Hi,I do not why I thought that reading from a PIO took a lot of time. If it takes only 3 clk cycles I can afford it and use two 32 bit PIOs instead of implementing something more complex such as a DMA & Avalon. Thank you for your help, XB