Required Nios components

[Altera_Forum]

Hello, 

I am trying to develop a very simple Nios cpu to run Hello world application. I have created a design:  http://i55.tinypic.com/a29isy.jpg  As You can see, I have inserted DDR2 memory to store required code. The whole system should run from altmemddr PLL. However, the EDS tool doesn't find neither sysid, nor timestamp. What is wrong with this design? I have tried to add timer, but that didn't help and afaik it is not required.  DDR2 pins are OK, I have taken them from a working example from development board CD.

[Altera_Forum]

--- Quote Start ---   DDR2 pins are OK, I have taken them from a working example from development board CD.  --- Quote End ---    Do you mean you tested the example on the same board? Or is this your custom board which pin locations have been copied from the dev board?  I don't think the problem is with ddr, since debugging tools should be able to get the correct sysid even if memory is not working. IMHO it's more probable the Nios is not working. Maybe a problem with input clock or reset signal. Are you sure the fpga has been correctly configured? Anyway I'd suggest this simple method to exclude ddr: you can temporarily replace it with onchip memory; this is enough for a "Hello world" kiind of program and it will let you take away any concern regarding external connections.

[Altera_Forum]

I have replaced the DDR2 memory with on-chip memory (262144 bytes), but the issue somehow was 125MHz clock. I have set the 50MHz clock instead and the Nios started. 

 The 125MHz clock was running for sure, I have made a blinker which works either with 125MHz clock or with 50MHz clock.  The development board is Cyclone III Host board from Altera (2 clocks on board + SMA IN)  Now the strange problem is that the console doesn't show anything. It runs the CPU:   --- Quote Start ---  Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Processor is already paused Reading System ID at address 0x00081030: verified Initializing CPU cache (if present) OK  Downloading 00040000 ( 0%) Downloading 00045CD0 (71%) Downloaded 24KB in 0.4s (60.0KB/s)  Verifying 00040000 ( 0%) Verifying 00045CD0 (71%) Verified OK  Starting processor at address 0x00040184  --- Quote End ---    I've checked BSP parameters, the stdin/stdout/stderr are all set to uart_jtag, but the console screen is empty.

[Altera_Forum]

Can you toggle a PIO from your Nios program? This way you may know if processor is running, independently from jtag uart operation. 

But first of all, is your design correctly time constrained? Did you get any critical warning during Quartus compilation? You must be careful with Nios designs using f>100MHz on CIII because timing problems can easily occur.

[Altera_Forum]

you can choose to ignore mismatched timestamp and sysid under run as -> run-configurations -> target connection

[Altera_Forum]

--- Quote Start ---  Can you toggle a PIO from your Nios program? This way you may know if processor is running, independently from jtag uart operation. But first of all, is your design correctly time constrained? Did you get any critical warning during Quartus compilation? You must be careful with Nios designs using f>100MHz on CIII because timing problems can easily occur.  --- Quote End ---   I will try to do that, but I've also tried to run debug. The output says, that the processor is started, but when the debug window comes up, I see the processor "terminated". I don't know why is this happening. There are 4 critical warnings because of constraints, but those are common and not familiar with Nios. Something like clock uncertainty on JTAG TCK pin, actually can't remember now the exact warning... In addition, Nios now runs on 50MHz directly from the clock, so should be fine.    --- Quote Start ---  you can choose to ignore mismatched timestamp and sysid under run as -> run-configurations -> target connection  --- Quote End ---    Yes, I know, but this is used for mismatched systems, that are familiar. E.g. You use somewhere compiled .sof file, but generate Your own Nios code. This feature doesn't work, when the core is not running. ID and timestamp fields are marked "Not found".   Thanks for the help.

[Altera_Forum]

hi guys ......... 

  socrates if your cpu run at 50Mhz and your ram run at 125Mhz you need to put a clock crossing bridge......  your problem seens to me a interface with your ram......  try put in you sopc   cpu -> clk 62.5 (altmenddr.halfrate)  jtag pio clock crossing bridge 62.5 -> 125 ram -> 125   this work fine  good luck    Franz Wagner

[Altera_Forum]

Well if You check the image I've posted in the first post, the whole system should run on 125MHz (clocked from altmemddr_sysclk). Only altmemddr instantiated PLL is feeded from external 50MHz clock, all other components, including memory and cpu, are feeded after the PLL from its output - 125MHz, so the system should work without clock bridge.

[Altera_Forum]

ok...... now i see..... 

  hum.....i have a cyclone iii dev board too....  i do a simple system to test and it works  starts with 50mhz all components and rise clock by steps  try do that   cheers  Franz Wagner

[Altera_Forum]

Are you sure the compiled design meet all timing requirements? In my experience it is difficult to make the NIOS CPU run over 100MHz without a pipeline bridge before the JTAG debug module. 

I agree with frantz... Try to run your system at 50MHz first, and then increase the speed from there.

[Altera_Forum]

Probably You're right. I have set the ddr controller to run at half rate (125MHz/2=62.5MHz), doubled the burst and now Nios runs fine, no need of pipeline bridge. 

 Thanks for help... Time to test SGDMA! Or maybe modular sgdma is better? Still confused, I need to transfer coded video data in packets to Nios, add IP header and proceed to TSE :)

[Altera_Forum]

--- Quote Start ---   I have set the ddr controller to run at half rate (125MHz/2=62.5MHz), doubled the burst and now Nios runs fine, no need of pipeline bridge.  --- Quote End ---    you can put your cpu and other peripherial (jtag pio etc) to work on 62.5 and your ddr2 to work on 125 (normally using clock crossing without pipeline).   if your cpu will work with clock over 65 mhz you NEED to put pipeline bridge........and peripherial does not work fine with high values of clocks..... is better you put cpu and ram to work with clocks over peripherials clock....   try it..........   cheers   Franz Wagner

[Altera_Forum]

--- Quote Start ---  In my experience it is difficult to make the NIOS CPU run over 100MHz without a pipeline bridge before the JTAG debug module.   --- Quote End ---     Hmmmmm... This is interesting to me. I have been having trouble getting text to display correctly on the Nios II Console using prntf() statements. A little text like "Hello World" display fine, but add more text and it stutters terribly. I've been thinking that it is probably due to JTAG UART timing somehow, but other features like SignalTap that us JTAG seem to work fine.  Could you describe how to insert a pipeline bridge in the JTAG Debug module interface? Maybe this would solve my problem.   Thanks in advance, I've learned a lot from your posts.

[Altera_Forum]

Add pipeline bridge to Your design and connect peripherals (like JTAG) to that bridge.

[Altera_Forum]

and dont forget conect the data slave and data master..........

[Altera_Forum]

--- Quote Start ---  and dont forget conect the data slave and data master..........  --- Quote End ---    I'm not sure I understand. Do I use one pipeline_bridge and connect its s0 to both the cpu data_master and instruction_master, then connect the pipeline_bridge m0 to the jtag_debug_module?   Or... Should I use two pipe_line bridge instances - one for the data_master and one for the instruction_master?

[Altera_Forum]

I'm not sure your problem is related to that. Does the problem disappear with a lower frequency? Did you run a timing analysis on your system? You should only add pipelines if your design doesn't meet timing requirements.

[Altera_Forum]

--- Quote Start ---  I'm not sure I understand. Do I use one pipeline_bridge and connect its s0 to both the cpu data_master and instruction_master, then connect the pipeline_bridge m0 to the jtag_debug_module?    --- Quote End ---      yes only one for data and instruction.......but i agree with Daixiwen ..I'm not sure your problem is related to that     if you rise frequence of cpu dont rise the frequence of jtag ......keep jtag uart with same frequence with it works and rise only cpu frequence ...   use a clock crossing bridge to do that.........   good luck ..   Franz Wagner

[Altera_Forum]

Thanks for all the great suggestions. 

 I constrained the design and ran a timing analysis which is fine. I changed the JTAG UART clock to 5 MHZ with the Nios II CPU running at 50 MHZ and a clock crossing bridge between them.  I also tried a pipeline bridge in series with the JTAG UART.  None of this made any change whatsoever to the corrupted text I'm getting on the Nios II Console.  I tested a similar Qsys design on the Altera Cyclone III Nios II NEEK and it runs fine - uh oh, something must be wrong with my board!!!  Here's the text I get on the NEEK:   <----> Nios II Memory Test. <----> This software example tests the memory in your system to assure it is working properly. This test is destructive to the contents of the memory it tests. Assure the memory being tested does not contain the executable or data sections of this code or the exception address of the system.  And this is what I get on my board running the same Memory Test app:   <<---- iissII eeooyyTTss.. <<----> hhssssffwwrr xxmmll eett hh eeooyyii oorrssssee ooaassrr ttii ookknn rrpprryy TTii eettii eettuuttvv ootteeccnneett fftteemmmmrr ttttssss ssuueetteemmmmrr eenn eettddddee oo oottii  the executable or data sections of this code or the exception addres fftteessssee..  

[Altera_Forum]

Do you have enough memory in your design? A collision between heap and stack could lead to something like this. 

Anyway if Timequest says the timing requirements are met then pipeline bridges won't change anything. I wonder if 5MHz isn't too low for the JTAG uart though.

[Altera_Forum]

My external SRAM is 516K by 16 bits, so I should be ok on size, right? I keep wondering about things like ground bounce, bad address and/or data lines, etc. as the memory chip is on an add-on daughter card. I've tested the memory with a straight hardware solution that did not involve Nios II or even Qsys. I've also tested it with System Console using a tcl script to exercise the SRAM. Also, when running a Nios II app the elf file always loads and verifies with no problem.  

 The corrupted text is always the same. I would think that a timing issue would yield variable results.  I've shifted the address lines and got exactly the same results. I may try shuffling the data lines to see what that does.  The 5 MHz JTAG UART was just a temporary test. Otherwise I have been running the entire system at 50 MHz. I do notice that if I crank up the system clock to 100 MHz it has trouble reading the System ID and Timestamp.