Running SDRAM at double speed

[Altera_Forum]

I currently have a NIOS1 design (but I think this will apply to NIOS2 as well) running at 60MHz, with 16 MB SDRAM. 

 The internal SOPC clock is PLL-ed to 60MHz and the E0 output (also 60 MHZ) is fed to the SDRAM ICs.   This works very well for my current application. BUT I now want to add a second master on the bus. This means (I think) that my 2 masters will now share the 60 MHz/ data bandwidth on the external memory.  Is there a way that I jack up the SDRAM speed to close to the maximum 133MHz and still have 2x 60MHz masters on the bus?  Thanks  Victor

[Altera_Forum]

Must the clock on the SDRAM be the same as the state machine's?

[Altera_Forum]

As far as I know, the frequency of the sdram clk equals to the cpu clock, can your Nios run at 120? 

Even if you can optimize your cpu to run at 120, I cannot remember where I had read an article said that the max frequency of the sdram controller is 100.

[Altera_Forum]

Even in the case of a max speed of 100MHz I will still gain performance (50Mhz x2). My gut-feel tells me that the Avalon bus will only wait until a transaction is completed. If the SDRAM controller finishes quicker then the Nios CPU and other master will run faster too. 

  The 2nd master can be another Nios, fully transparent VGA running off main memory or any master that regularly requires memory at close to full speed.  Victor

[Altera_Forum]

In my tests with my custom Cyclone board, I found that I could run out of onchip ram to 140MHz, run out of onchip but use SDRAM for data to 120MHz. I could use SDRAM for instruction and data to 112MHz. 

 On my board, I required only one PLL (CPU and SDRAM share) with no delay. I placed the 16MB SDRAM module close to the Cyclone and routed every signal on the top layer.  Ken

[Altera_Forum]

Ken 

 My problem is that I am already sitting with current boards running at 60MHz. They actually top-out at 75 MHz. The reason why I don't go faster is power. The boards were designed with Nios1.2 in mind and then upgraded with NIOS1.3 with the old SDRAM controller. These boards ran at 40MHz. With a few tweaks I got the 60 MHz. I can go a bit faster but then my PSU, designed with the requirements at 40MHz, goes out of spec (1.5V side).  So I am stuck at 60MHz max. What I need is an onboard VGA controller. This will be a master sharing memory with my main NIOS master. To do 640x480 @ 60Hz the VGA controller will take up about 18 MHz bandwidth if everything goes its way. To reduce losing speed on my NIOS side I feel that I must keep the core at 60MHz, run the SDRAM at 100MHz and have about 20MHz BW spare. Looking at the documents it looks like the SDRAM must be in sync with the Avalon bus.   IF ... the Avalon bus can only start the transaction and wait for a busy signal to fall away it means the SDRAM controller can run at whatever speed it wants, doesn't it? My PC has a CPU speed of 2.5GHz, FSB of 400MHz and 400MHz memory. This holds true for two or more NIOS CPUs running at the same time. If you can run from cache it is cool, but if both masters move large blocks of memory then there is only one pipe running at X Hz. Thus 2 CPUs running at 50MHz from the same 50MHz SDRAM do not run as well as 2 from SDRAM clocked at 100MHz. I just feel it is a waste. Infact I am using PC133 spec.   Somehow some device must be able to wait for something?  Victor

[Altera_Forum]

Victor, 

 I don&#39;t know the answers to the question(s) you&#39;re asking, but since those who do are silent I will make some suggestions. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif   You may be able to do what you want through trickery.  Run your CPU/System at 50MHz, and run the clock to your SDRAM at 100MHz. Your SOPC will still say 50MHz so you may/will need to adjust the timing settings in the SDRAM controller wizard. Since the timings are going to map to a number of clocks not ns you can raise the values until it works. (Or lower them until it breaks)  Basically you should be able to get the 50MHz bus to to wait fewer 50MHz clocks because the mem is actually going to be done in half the time. If 50/100 draws too much power, try 40/80. I&#39;d keep it a 2X multiple.   Can&#39;t hurt to try.  You also might actually verify the situation with Nios2 since it may have a little different power draw? And if you have any LED&#39;s lower the current and try to not toggle any lines that you don&#39;t really need to.  Ken

[Altera_Forum]

So the Avalon bus will be the bottleneck..Hmmm. 

 So what I really need to do is to run the bus at 100Mhz and NIOS at 50Mhz. If I can do this NIOS will only use 1/2 of the bandwidth and leave the rest to other devices. I think this is do-able, don&#39;t you?  If a NIOS cpu only requests access for half the bus cycles the avalon bus should, in theory, give it half the access it wants. The same holds true for the current 1:1 condition. If 2 NIOSs run off a 50MHz bus at full speed, with no cache, then the access to the memory, for each, will average out to about 25MHz BW.    For NIOS 1 this is easy to do because I have the source. I also have to tweak the other devices like the UARTs. If NIOS only asks for access every 2nd clock then it will only run like a 50MHz CPU with a 100MHz clock. For the 2nd master I probably need to do a 180 degree clock shift to ease out the bus, maybe not...   I believe that this is going to become more important as time goes on. Ken, you commented the following:"i found that i could run out of onchip ram to 140mhz". If you could use DDR memory at 266MHz equivalent then it means that best case your system is only using 140MHz of it. DDR gives you the chance to run at 133 for 266 but still to execute 140MHz equi you need to run 140MHz. Memory will get faster DDR2- QDR etc... Somehow there must be an easy way for multiple NIOSs and other masters to run at full speed in parallel?  Bottlenecks! The easy answer is put multiple sections of memory on the board, but many designers opt for the simplest design and or cheapest. If you sit with a design like mine that tops out at 75MHz(and with many boards in the field) and you have memory that SOPC can use at 100MHz, at least, then it means that there is room for improvement.  So why the hell do I want to do what I want to do? Currently just shared VGA running off main memory. I also have another application. I am doing business with systems integration company. Their flagship product is designed and maintained by 5 entities, including themselves. They spend small fortunes on integration tools like custom networks and simulators. I proposed a NIOS system whereby there are 5 main NIOSs on one chip. The majority of the magic happens with memory blocks shared between the systems. So it makes sense that everything runs off one block of memory. They will physically save millions in R&D. Each company has its own serial download and debugging interface and I/O ports.  Some of the apps only need small amounts of CPU power, like MMI. Others like the motor control needs DSP control loops and will probably require about 70% of the clock resources. This means that if I can run a StatixII at 200MHz I will at default have about 40MHz per CPU memory bandwidth.   So here is what I propose: * SOPC is still spec-ed with a global frequency (so all the UART goodies runs from a stable source) * All other masters have a clock divider function (not just priority). (Thus any master like a NIOS, DMA or custom master). A NIOS can be programmed to run at full speed (undivided) or fractions.   This means if 2 NIOSs are clock divided by 2 the example above they will run at 100MHz each. BUT you won&#39;t gain anything !!! Yet. But if you look at your memory you will notice that your DDRs can move 266Mega words per second. Thus with a divider of 2 you can run each to a max of 133MHz.   Now add a small NIOS2e CPU for a stupid MMI controller with a LCD and key interface. On the current method this poor bugger will try to run at 1/3 the speed (shared between e.g. the two other NIOS2f CPUs). You probably only need a 10MHz CPU tops. So for this one you will divide its clock by 16. So although your main clock can be about 200MHz your NIOSIIe will only run at 12.5Mhz. Also using less power.    This will several advantages: * Power * Loading * Keeping certain NIOS blocks close to a standard execution time . * Using faster memories -> More NIOSs per chip -> No degradation in performance.    Victor