Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
1,228 Views

Running separate C code on separate core in NIOS Multi-core system

Hello, 

 

I have done projects on NIOS II core for single processor system. 

Now, I need to learn and implement a multi-core system.  

 

I have very basic doubts for a multi-core system: 

 

1. If I have two independent cores. How to run separate c codes on that two core ?? And that two codes should start simultaneously. 

Is it compulsory to make one core as Master to start the another core?? 

2. If I have dependent cores, How to communicate between two cores?? While communicating with a slave peripheral, we generally knows the address for diff registers in slave device and use to specify that address during Avalon MM interface. But if i want to send some data from one core to another, what are all the option and how ?? 

 

Please Suggest. 

 

-Anuj
0 Kudos
11 Replies
Altera_Forum
Honored Contributor I
25 Views

I have been following the Philosopher tutorial from the altera website. In that, the software projects are created, compiled, and executed by script. Also the terminal is opened by script. But how to do that for our own custom project. Are their options other than script ??  

 

Do i need to write script for that?? or i have options from Eclipse SBT ?? 

 

Please help
Altera_Forum
Honored Contributor I
25 Views

 

--- Quote Start ---  

or i have options from Eclipse SBT ?? 

--- Quote End ---  

 

 

The "Philosopher" tutorial ( http://www.altera.com/literature/tt/tt_nios2_multiprocessor_tutorial.pdf ) walks you through debugging the software from within Eclipse. 

 

On page 1-33, the section titled "Debugging the Applications in the NIOS II SBT for Eclipse"
Altera_Forum
Honored Contributor I
25 Views

You need to think about how the code (etc) will get loaded into the memory areas. 

If you plan loading from EPCS then only one nios can run the boot code. 

I'm not sure about JTAG, but having one copy is probably easier. 

We load code over PCIe - so can have completely separate nios systems, they are released from reset over the pcie. 

 

If you have 2 nios that are cooperating, it is probably easiest to compile and load the code as a single image - that way you don't have to worry about the actual addresses of items in shared memory. Use the gcc __attribute__((section("section_name")) and a custom linker script in order to get everything at the right physical addresses. 

The startup sequence is probably safer if one nios starts the other (eg after zeroing the bss and initialising other shared memory) even if you don't need the nios running in order to download the code. 

 

You'll need a short asm stub for the second nios to initialise the global registers (%sp, %gp and maybe the interrupt temporaries) before jumping to a C function. It is any of libc (eg printf) things are more difficult! 

 

For inter-nios communication use internal M9K memory blocks, tightly couple it to one nios and access from the other as an avalon slave (uncached). If you don't need access from anywhere else you can tightly couple to both nios. 

Make absolutely sure the shared memory is running from a single clock and has 'old data' selected for concurrent access (need qsys). 

 

For interlock use Dekker's algorythm,
Altera_Forum
Honored Contributor I
25 Views

Hi, 

 

I am trying following the philosopher tutorial and creating my own project. I am facing following difficulties: 

 

1. I made two subsystem same as given in philosopher tutorial (includes NIOS, JTAG, 3 Avalon Bridge, Mutex). When i include this subsystem in my top system(includes 2 Subsystem as describe earlier, Onchip Memory, Jtag Uart, NIOS), I get an error saying "the onchip memory is out of memory space defined for NIOS master port".  

And I can see that, the address assigned to on chip memory is unreachable by the no of bits assigned to the address bus of NIOS Master Port. As i increase the bit size of address bus of NIOS master port, the on chip memory address also increases and again goes unreachchable. 

 

What should i do for this case?? 

 

2. I want to know the difference betwn Avalon MM Data Master Port and Avalon MM Instruction Master Port. 

Which out of these should be connected to Onchip Memory, JTAG UART, custom block, performance counter and WHY ??? 

 

Suggestions and help is highly appreciated. 

Thanks
Altera_Forum
Honored Contributor I
25 Views

 

--- Quote Start ---  

Hi, 

What should i do for this case?? 

 

--- Quote End ---  

 

 

Post a .zip with your subsystem .qsys and toplevel .qsys 

 

 

--- Quote Start ---  

 

2. I want to know the difference betwn Avalon MM Data Master Port and Avalon MM Instruction Master Port. 

Which out of these should be connected to Onchip Memory, JTAG UART, custom block, performance counter and WHY ??? 

 

--- Quote End ---  

 

The instruction master is used for fetching instructions. 

The data master is used for performing data operations (reading/writing variables your program uses, reading/writing peripheral control registers). 

 

Connect the instruction master to the memory where your program is located. 

Connect the data master to (basically) everything including the program memory.
Altera_Forum
Honored Contributor I
25 Views

Hi here i am attaching my zip file of project. 

It has two .qsys files. One is the the subsystem which is instantiated twice in the top level design.
Altera_Forum
Honored Contributor I
25 Views

Error: System.core0_0.p1_out: core0_1.pi_in (0x400000..0x5fffff) is outside the master's address range (0x0..0x1fffff)  

 

Your master has an address space that is 21-bits wide (because that is how you created the bridge). 

 

You are connecting it to a slave that requires 23-bits to address it. 

 

 

If you change your master to have an address space that is 23-bits wide, you will not have a problem.
Altera_Forum
Honored Contributor I
25 Views

Error: System.core0_0.p1_out: core0_1.pi_in (0x1000000..0x17fffff) is outside the master's address range (0x0..0x7fffff) 

Error: System.core0_1.p1_out: core0_0.pi_in (0x1800000..0x1ffffff) is outside the master's address range (0x0..0x7fffff) 

 

This is what I got when i changed the address space of my bridge to 23 bits.
Altera_Forum
Honored Contributor I
25 Views

My suggestion is that you change the address space of your MASTER. 

 

You appear to have changed the address space of both your MASTER and SLAVE. 

 

Try just changing the MASTER to have the wider address space and leave the SLAVE alone.
Altera_Forum
Honored Contributor I
25 Views

Thanks ted, that worked. 

 

Now, when i am trying to make a new project in NIOSII SBT for Eclipse by importing the .sopcinfo file, I get 3 CPU names on the list as I have total 3 cores in my Qsys system. 

 

But when I select any one of them, it throws an error: 

"Failed to execute: ./create-this-bsp --cpu-name nios2_qsys_0 --no -make" 

 

I select the top level *.sopcinfo file.
Altera_Forum
Honored Contributor I
25 Views

If you google that error, you get this knowledge base article which may be relevant to you: 

http://www.altera.com/support/kdb/solutions/rd10082010_852.html