SOC CyV ARM and ethernet connection

Nios® V/II Embedded Design Suite (EDS)

Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++

SOC CyV ARM and ethernet connection

1,019 Views

i've TERASIC NANO/ATLAS DE0 KIT,

how can i assume a connection to send UDP data packets from FPGA throught HPS ETHERNET connecion?

Ethernet PHy is connected to HPS, no to FPGA.

some approach?

I'm using LINUX NANO IMAGE, "POKY" with framebuffer.

Thanks.

Link Copied

0 Replies

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.