Hello All,
I am very new to this Qsys environment. I developed a adder circuit and would like to develop it as a component in the Qsys environment. I created a new component, entered my verilog adder file, synthesized it without errors. I am stuck with the "Signals" and "Interface" part. My adder has 3 inputs, a,b,cin with sum and carry without any clock or reset. I would like to know how I can create a "Signal/Interface" for this. What interface I should use? I tried with "new_avalon_st_source for "sum/cout", "new_avalon_st_sink" for "a/b/cin", but getting errors. Can someone help me? Thx, RNLink Copied
Where is the component supposed to be connected?
If the adder i/o data serves a component with an Avalon ST interface, you indeed use avalon ST source/sink. On the other hand, if you want to access it from Nios, you usually create a custom instruction or a MM slave interface. In any case, the interface behaviour is defined by verilog code: you can't simply assign signals in Qsys; if that interface is actually not implemented in the design you'll get errors.Hello,
Thanks a lot for the information. Is there some document or examples that shows how to develop new components from verilog files and integrate in NIOS II. I have small designs like ripple carry adder, decoders, counters and other circuit written in verilog and I want to connect to NIOSII. I appreciate your help. Thx, RNThere's indeed a lot of documentation on this subject. Browse the Altera website and the forum.
You may start with the Qsys manual, in particular this section: http://www.altera.com/literature/hb/qts/qsys_components.pdf Anyway, if you need to integrate in Nios the small specific functions you pointed out, I'd implement as custom instructions.For more complete information about compiler optimizations, see our Optimization Notice.