Nios® II Embedded Design Suite (EDS)
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12500 Discussions

probleme with qdrii, please help

Honored Contributor II


I am using stratix iv and quartus 10.1.  

my project compile without any error, but when I run DDR report for my ddr3 and qdrii in timequest timing analizer, it works for ddr3 but not for qdrii, I have this error : 


warning: Ignored filter at uniphy_qdrii_report_timing_core.tcl(197) : my_inst........ could not be matched whit a keeper or register or port or pin or cell or net  


Missing required positional arguments: <body> 


Usage: foreach_in_collection [-h | -help] [-long_help] <variable_name>  

<collection> <body> 

-h | -help: Short help 

-long_help: Long help with examples and possible return values 

<variable_name>: Variable name 

<collection>: Collection 

<body>: Body 


I find in altea that to solve this proble (the example speeks about DDR3) I must select auto leveling. I don't know how to select this in sopc builder I didn't find any thing refering to that. 

Please help !!!!
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