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Anyone else using the Stratix II DSP Kit?

Altera_Forum
Honored Contributor II
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Hi all, I have a Stratix II DSP kit that I will use to test out some DSP algorithms. However, first I want to boot a NIOS processor and get the simple socket server test running. I want to be able to transfer the results of a test over ethernet to a control computer. 

 

The DSP kit does not ship with a 'standard' reference design, so it looks like I'll have to start with the NIOS II/Stratix II development kit reference design, and adjust pin assignments. The DSP kit ships with a 100MHz clock, so I figure I'll use the PLL to reduce it to 50MHz. 

 

Anyone else already dealt with these issues?  

 

Regards, 

Dave Hawkins. 

Caltech.
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Altera_Forum
Honored Contributor II
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Hello Dave, 

 

Which version of CD do you have with your DSP kit? On StratixII_DSP_Kit-v1.1.0 CD I have all reference designs: fast, full_featured, small, and standard. Maybe you should upgrade your software. 

 

I also just sturted playing with this kit. My idea is to test my cores in FPGA and present the test results on www. 

 

Regards,
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Altera_Forum
Honored Contributor II
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Hi, 

 

I am using StratixII-ep2s60-dsp-development-board. 

 

this board is now communicating with vcc++-program over tcp/ip. 

 

nios2 program size is too large(380KB), so it is located in cfi-flash memory. 

(i need on-chip memory to design image-processing-ip) 

 

if you have the same problem, you should make the flash_writer_circuit 

 

to download program into flash, 

 

and also you should make "target board" to create actual nios2-cpu. 

 

flash boot address is: 

factory: 0x200000 

user1 : 0x500000 

user2 : 0x800000 

user3 : 0xc00000
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