Avalon -> Dual Port RAM -> custom hardware interface

[Altera_Forum]

Hi All, 

 I am creating a custom memory mapped device and need to create an 8k byte block of dual port RAM with write-only access from NIOS, and read-only access from the custom hardware side.  RAM needs to be internal to the Cyclone IV FPGA.  I have found a dual-port Avalon memory part within SOPC builder, but feel that I don't need anything quite as elaborate as Avalon on the custom hardware side.  Having said that, the custom hardware will be reading a byte every 8th clock cycle at 50Mhz, so I will need the Avalon / NIOS side to generate wait states should a bus conflict occur.  Any pointers appreciated before I go-chasing-my-tail for a week.  Many thanks,  Mark

[Altera_Forum]

Creating what you want is as simple as the attached - a VHDL 'interface' that contains the mapping from Avalon signals to RAM signals. Use the component generator to build a _hw.tcl and export the ram_xx signals as a conduit. You can then instantiate the RAM and the control logic on the other port of the RAM outside the SOPC/Qsys system. 

 Cheers, Dave

[Altera_Forum]

Many thanks Dave, 

 That attachment is very well documented and should be a good starting point  -Mark