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Booting from offboard CFI directly connected to FPGA

Aflop
Beginner
942 Views

Hello, 

 

I am new to FPGA's and have been handed an assignment which I am not sure is possible.

I have a Cyclone 10 GX Development Kit which must get configured with a NIOS and booted with application code from CFI memory which is connected to the Cyclone 10 via the FMC.

I have been following:

https://www.intel.com/content/dam/support/us/en/programmable/support-resources/fpga-wiki/asset03/nios-ii-processor-booting-from-cfi-flash.pdf     

 

BUT the document describes a scenario where the CFI is connected to the CPLD which is not my situation. I am not sure how to proceed after page 16 when I need to instantiate a PFL on the the dev kits Max 10. The PFL inputs and outputs require pins which are located on the Cyclone which confuses me.

1.) Is my current plan of action feasible? If so, how do I wire the PFL such that it flashes the CFI with the correct data?

 

2.) If this plan is not feasible are there any alternatives, given the limitation that the Cyclone 10 must boot from offboard memory?

 

Thank you  

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1 Solution
FvM
Valued Contributor III
804 Views

Hi,
both AS and PP configuration interface are using dedicated FPGA pins and can't be replicated on other pins. That's because the specific function is built-in to the FPGA, working before any user code has been loaded. NIOS boot is controlled by HDL code and can basically use any memory interface.

While AS configuration is performed autonomously by FPGA, PP needs an external controller, usually MAX V CPLD. Configuration data is presented to FPP data lines (either 16 or 32, depending on the mode) and clocked in by DCLK.

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7 Replies
Aflop
Beginner
904 Views

If there is any information that I unintentionally left out or there is more context that I could provide, please let me know. I am still working on finding a solution to this. 

To be clear I have a Cyclone GX 10 dev kit which is connected to a proprietary board using the FMC connector. On this board is a QSPI chip and a CFI chip. I am trying to configure the Cyclone 10 FPGA and boot a NIOS from either of these chips.

From everything I have been reading, it is uncommon for the memory devices to be connected to the Cyclone 10 FPGA but not the Max 10 or a CPLD which orchestrates the configuration process. 

Hypothesis 1.) FPGA configuration is not possible without the offboard memory being connected to the Max 10. 

Hypothesis 2.) Booting NIOS from offboard memory should be possible given correct memory vectors and tristate controller / bridge.

 

If anyone has any thoughts on this, it would be very helpful. As I said, I am new to FPGAs and the only evidence I have to support my hypothesis is that I cannot find any examples where the FPGA is configured from memory that is not connected to a CPLD or Max 10 device. Likewise, I have not seen the NIOS booted from memory which is not connected to a CPLD or Max 10 but intuitively believe it would be possible based on the capabilities stated in the "Booting from CFI" tutorial in the main post.

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Jeet14
Employee
857 Views

Hi,


Thanks for contacting Intel. I'm assigned to support request.

I'll investigate on this case and get back to you soon once I have any finding.

Thanks for your patience.


Regards

Tiwari


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FvM
Valued Contributor III
832 Views
You say, you want to connect QSPI and CFI memory though FMC connector. However FMC doesn't regularly include active serial or passive parallel configuration signals. In so far I don't see an option to perform FPGA configuration through the interface. Reading and writing CFI should be possible.
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Aflop
Beginner
822 Views

FvM,

 

Thank you for your response. If I am understanding you correctly, even though we are replicating the CFI and QSPI interface over FMC, there is no way to configure the Cyclone 10 using this interface?

For example could we not use the the Generic Serial Flash Interface IP to define a new configuration interface over the FMC connector?

Additionally, for configuring the Cyclone 10 using CFI wouldn't we need to use a passive scheme? From my research, passive configuration schemes seem to require a CPLD or in the case of the Cyclone 10 GX dev kit, a Max 10. Is this correct?  

 

Thank you

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FvM
Valued Contributor III
805 Views

Hi,
both AS and PP configuration interface are using dedicated FPGA pins and can't be replicated on other pins. That's because the specific function is built-in to the FPGA, working before any user code has been loaded. NIOS boot is controlled by HDL code and can basically use any memory interface.

While AS configuration is performed autonomously by FPGA, PP needs an external controller, usually MAX V CPLD. Configuration data is presented to FPP data lines (either 16 or 32, depending on the mode) and clocked in by DCLK.

Aflop
Beginner
769 Views

FvM,

 

Thank you for your answer. This cleared up a lot for me.

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Jeet14
Employee
726 Views

Hi,


I saw that your query has been answered by our another valued customer on forum and the answer has been accepted. Thanks to FvM for helping.

Let me know if you have any question on this matter.


Regards

Tiwari


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