DSP Builder & SOPC Builder Workflow

[Altera_Forum]

Hi  

I'm working on the DSP Builder SOPC Builder Designflow.  1. I have built a DSP Builder Model in Matlab Simulink with a Avalon Interface. 2. Create the SOPC Builder Block with nios, memory...  Simulating "Hello word" works in Modelsim 3. I add my DSP Builder generated AvalonSlaveTest in the SOPC Builder  Generating the SOPC System works without a problem 4. Again i want to simulate my HelloWord example in the Modelsim  With the command "s" i compile the generated HW in Modelsim. I get the error# **Error:(vcom-19) Failed to access library 'dspbuilder' at 'dspbuilder# No such file dor directory(errno=ENOENT)  I konw my library dspbuilder is missing, but way?? DO i have to add this library by my own? How does this work?  I hope anybody can help me! thanks mfg florian

[Altera_Forum]

--- Quote Start ---  originally posted by fplank@Jun 7 2006, 12:33 AM hi  i&#39;m working on the dsp builder sopc builder designflow.  1. i have built a dsp builder model in matlab simulink with a avalon interface. 2. create the sopc builder block with nios, memory...     simulating  "hello word" works in modelsim 3. i add my dsp builder generated avalonslavetest in the sopc builder     generating the sopc system works without a problem 4. again i want to simulate my helloword example in the modelsim  with the command "s" i compile the generated hw in modelsim. i get the error# **error:(vcom-19) failed to access library &#39;dspbuilder&#39; at &#39;dspbuilder# no such file dor directory(errno=enoent)  i konw my library dspbuilder is missing, but way?? do i have to add this library by my own? how does this work?  i hope anybody can help me! thanks mfg florian <div align='right'><{post_snapback}> (index.php?act=findpost&pid=15988)  --- quote end ---    --- Quote End ---    Hi mfg florian,  There are two things you need to get the DSP Builder components to simulate in modelsim.  1) Update the setup_sim.do file to find the dspbuilder library 2) Double check the order of your VHDL files in the setup_sim.do file to make sure those files are compiled bottom up.  NOTE: Make back up of the setup_sim.do file. Every time you re-generate your SOPC Builder system it will OVERWRITE the setup_sim.do file.  Here are the details on how you can do the two steps:  In the project directory there is a sub-directory called sopc_sim. This is where the modelsim set up files are located. The setup_sim.do file is the modelsim macro file that sets-up the modelsim simulation. You will need to edit that file to add in the dspbuilder library information.  I recommend looking at the test-bench setup tcl file generated by DSP Builder tb_<your_dsp_builder_component_name>.tcl. This tcl file has all the settings to do a unit test of your DSP Builder component in modelsim.  In that tcl file you will find the location of the dspbuilder library.  Example: set libdir "c:/altera/DSPBuilder/altlib" set megadir "c:/altera/dspbuilder/MegaCoreLib"  And the tcl commands to compile the dspbuilder library in modelsim:# Compile dspbuilder VHDL library  if {([file exist dspbuilder] ==0)||($bForceRecompile>0)} {  exec vlib dspbuilder  vcom -93 -explicit -work dspbuilder "$megadir/SignalTapNode.vhd"  vcom -93 -explicit -work dspbuilder "$libdir/dspbuilderpack.vhd"  vcom -93 -explicit -work dspbuilder "$libdir/dspbuilder.vhd"  } exec vmap dspbuilder dspbuilder  You will need to add the vmap and vcom commands to the setup_sim.do file.  NOTE: The .do file is not a tcl file so don&#39;t cut and paste the tcl commands directly!  The modified setup_sim.do file should look something like this with the added lines: # set path location variables at top of file set libdir "C:/altera/DSPBuilder/Altlib" set megadir "c:/altera/dspbuilder/MegaCoreLib" . . .  vmap lpm work  vmap altera_mf work  vmap sgate_pack work  vmap sgate work  vcom -93 -explicit c:/altera/quartus51/eda/sim_lib/altera_mf_components.vhd  vcom -93 -explicit c:/altera/quartus51/eda/sim_lib/altera_mf.vhd  vcom -93 -explicit c:/altera/quartus51/eda/sim_lib/220pack.vhd  vcom -93 -explicit c:/altera/quartus51/eda/sim_lib/220model.vhd  vcom -93 -explicit c:/altera/quartus51/eda/sim_lib/sgate_pack.vhd  vcom -93 -explicit c:/altera/quartus51/eda/sim_lib/sgate.vhd   vmap dspbuilder dspbuilder  vcom -93 -explicit -work dspbuilder $megadir/SignalTapNode.vhd  vcom -93 -explicit -work dspbuilder $libdir/dspbuilderpack.vhd  vcom -93 -explicit -work dspbuilder $libdir/dspbuilder.vhd  (The colored sections are the added lines to the setup_sim.do - I hope it will be clear where to put the new lines)  After you get the library set-up done you should check the order of the VHDL files are compiled from the bottom up. You can verify the order from the tcl unit test setup file. If the files are in the wrong order make the adjustments to that section of the setup_sim.do file.  From what I can tell the DSP Builder’s generated class.ptf file (found in the component’s sub-directory) has the files listed from top down (which is the incorrect order). You could edit the class.ptf to get the files to be listed from the bottom up, but always back up that file before editing them.  This should get modelsim to load the DSP Builder generated component.  Good luck and let me know if you get things working.  Regards, ATJ