FIFO - Transfer of data

[Altera_Forum]

IS there anyway to transfer data in\out of the SOPC FIFO instantiated core to logic outside of the SOPC sytem without using a NIOS ? It seems from the datasheets of the core that the only way to access this type of FIFO is via commands from a uP ?

[Altera_Forum]

You just need a read or write master to move data in and out of the FIFO. You can also use streaming sources and syncs to move data back and forth. This is what you would use for the various configurations:  

 Send data outside of SOPC Builder:   Master --> |Slave FIFO Export| ---> Outside SOPC Builder  Source --> |Sink FIFO Export| ---> Outside SOPC Builder  Send data into SOPC Builder system:   Outside SOPC Builder ---> |Export FIFO Slave| ---> Master Outside SOPC Builder ---> |Export FIFO Source| ---> Sink   The |xxxx FIFO xxxx| is supposed to represent the ports you should use to accomplish this. To see how you should hookup the FIFO signals to the ports I recommend instantiating the FIFO components that comes with SOPC Builder and see how the signals map (generate the system to see the HDL). You'll find the logic maps very well just using empty/full to map to !ready and waitrequest.

[Altera_Forum]

Dear BadOmen, 

Thank you so much for your help. Could you please explain a in a bit more detail what you wrote :-   "Master --> |Slave FIFO Export| ---> Outside SOPC Builder Source --> |Sink FIFO Export| ---> Outside SOPC Builder Send data into SOPC Builder system: Outside SOPC Builder ---> |Export FIFO Slave| ---> Master Outside SOPC Builder ---> |Export FIFO Source| ---> Sink The |xxxx FIFO xxxx| is supposed to represent the ports you should use to accomplish this. To see how you should hookup the FIFO signals to the ports I recommend instantiating the FIFO components that come with SOPC Builder and see how the signals map (generate the system to see the HDL). You'll find the logic maps very well just using empty/full to map to !ready and waitrequest."    I am sorry I didn't really understand it

[Altera_Forum]

oops I keep forgetting to enable jscript.... 

 I reformatted my original post so hopefully it makes more sense. There are various port types you can use in SOPC Builder, masters and slaves for MM, sinks and sources for ST, and export for exposing signals to the top. I'm not sure what you are trying to do so I can't make a recommendation on whether MM or ST is more suitable so I would look at the Avalon specification on the SOPC Builder literature page and determine which interface type is more appropriate for your FIFO component.