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Hello All,
I am new to Altera CPLD's (I am a Xilinx/Atmel guy) and need some support really fast. I have been asked to figure out why my predecessors design will not program via the ISP header. I have been looking through the datasheets and to me it looks like this chip does offer that functionality since it is not a MAX7000S family member. Can anyone confirm/deny my hasty conclusion? Thanks, KipLink Copied
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