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Interface to dual port ram memory

Altera_Forum
Honored Contributor II
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Hi,  

 

I want to access (read/write) dual port ram in my sopc system. How could I do that in my Nios II program?  

 

Thanks, 

Caridee
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Altera_Forum
Honored Contributor II
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You can use either the IORD/IOWR macros, or directly use C pointers. In the latter case, you must go through the alt_remap_uncached() function to define your pointer, to be sure you bypass the data cache.

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Altera_Forum
Honored Contributor II
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Hi Daixiwen, 

 

Thanks alot for your reply. I'd appreciate your help again if you could give me sample of C code using both MACRO and pointer methods to say for example write data to dual port ram address through Nios II cpu. 

 

Thanks in advance. 

 

Regards, 

Caridee 

(http://www.alteraforum.com/forum/member.php?u=4443)
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Altera_Forum
Honored Contributor II
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Through the IOWR macro: 

IOWR(YOUR_DPRAM_BASE,reg,value) 

Where reg is the 32-bit register number (reg = 0 will write at YOUR_DPRAM_BASE, reg = 1 will write at YOUR_DPRAM_BASE+4, etc...) and value is the 32-bit value to write. 

Using pointers: 

int *myPointer = (int*)alt_remap_uncached(YOUR_DPRAM_BASE,YOUR_DPRAM_SPAN); myPointer = value1; myPointer = value2; 

etc...
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Altera_Forum
Honored Contributor II
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Hi Daixiwen, 

 

Thanks for the codes... i will try it out... 

 

by the way, i am a abit new in using macro. can u pls explain to me why  

reg = 0 and reg = 1 are differ from 4 bytes?  

 

Thanks again, 

Caridee
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Altera_Forum
Honored Contributor II
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The IORD/WR macros read and write 32-bit registers directly. That's why when you increase the register number by one, the macro will access the next 32 bits, i.e. the next 4 bytes.

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Altera_Forum
Honored Contributor II
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I am using the On-chip memory (RAM or RAM) in my design. This memory component is described briefly here (http://www.altera.com/literature/hb/qts/qts_qii54006.pdf) (Page 9-6), but I was wondering if there is a more detailed document? I could not find any. 

 

this (http://www.altera.com/literature/hb/nios2/n2cpu_nii5v3_02.pdf)document describes a FIFO memory core, but that's not the one I am using.
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Altera_Forum
Honored Contributor II
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I don't think there is any other document about the on-chip RAM.

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Altera_Forum
Honored Contributor II
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Hello Daixiwen, 

 

Thank you so much for your explanation.  

 

Caridee
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