Just wanted to make sure of some things..

[Altera_Forum]

Hello, 

 Recently I got a hold of a NiosII Evaluation kit, and just had a couple questions on what is possible or not with an embedded fpga system like this with a processor. I have worked with FPGAs before to make things such as ADC programs and misc DSP stuff in logic, but havent worked with one with linux running on it as well.   Is it possible to run the uClinux distro on it, and as well have stand-alone FPGA programs running as well?  An example would be me running an ADC program on the FPGA, get that data into a register or output pin, and have linux read those registers/pins, and then in turn, output it via ethernet. (tho the linux->ethernet is somthing ill have to work on later, now im working with just getting it somewhere so linux can read it)  Thanks for any help anyone has to offer to clarify this for me, -Mark

[Altera_Forum]

Hi Mark, 

 > Is it possible to run the uClinux distro on it,  Yes.  > and as well have stand-alone FPGA programs running as well?  I'm not sure what you mean by "stand-alone FPGA programs" ... but here goes:  -Yes, you can write your own applications that run under uClinux. -Yes, you can write your own applications that use the HAL (no Linux). -No, you can't run them at the same time.  > An example would be me running an ADC program  ... snip ... > and then in turn, output it via ethernet.  Yes, this is where uClinux and Nios II are a great match. You can do this with a simple device driver and a simple application. You could even setup the web server to monitor data via a browser.  Regards, --Scott

[Altera_Forum]

Thanks Scott! 

 Though, the ADC that I would be running would be going at a rate of about 100 mega samples per second (and faster once we get out of the evaluation boards and into somthing faster).   Normaly on an FPGA that would have a 100MHz clock, this would be perfect, but with linux running as well, would the timing be lagging? Or is it simply just that I could write the program for linux, and would run at this clock speed. Basicly asking if its a real-time operation like how a FPGA would be programmed.  And just to clarify, when I meant ADC, I mean the ADC chip itself incase you were thinking of another board with a differnt type of protocol. Im not sure if you took it as that or not, but just wanted it out there to be sure.  Im suprised that linux and another FPGA program cant be running at the time, since FPGAs can run parallel tasks, and I doubt it takes up 100% of the gates running, tho.. im sure there might be more technical details that im unaware of.  Thanks again! -Mark

[Altera_Forum]

Hi Mark, 

 > the ADC that I would be running would be going at a rate of about 100 mega samples > per second (and faster  Assuming even a meager 8-bits/sample, that's > 800 Mbps ... you better start thinking about something faster than Gigabit Ethernet!  > Normaly on an FPGA that would have a 100MHz clock, this would be perfect, but with linux running > as well, would the timing be lagging? Or is it simply just that I could write the program for linux, and > would run at this clock speed.   I guess you haven't done the math ... I don't think linux will be your primary constraint ;-)  > Im suprised that linux and another FPGA program cant be running at the time, since FPGAs can run > parallel tasks, and I doubt it takes up 100%  Don't be surprised. You're mixing apples and oranges here. Linux is not an "FPGA program" ... it's not a digital circuit ... it's software ... a collection of opcodes and associated data that are executed by a stored program computer ... in this case the Nios CPU. You can have as many "FPGA programs" as you can fit on your FPGA. If one or more of them happen to be a Nios CPU, you can "run" linux on the Nios CPU(s).  Regards, --Scott

[Altera_Forum]

Hi Scott, 

 >Assuming even a meager 8-bits/sample, that's > 800 Mbps ... you better start thinking about something faster >than Gigabit Ethernet!  For the application that Im going to be using it for, it would have it be counting pulse width, height, and frequency, so I wouldnt need to be sending a stream of this data over the ethernet, just a numbers after it has been sorted out on the FPGA side.  Thanks for clearing up the FPGA / linux stuff, but I still feel lost on how its all setup on this board and whats runnning and where, etc. But Ill check into it a bit more later on, certainly have enough docs on it.  Thanks for your help! -Mark

[Altera_Forum]

--- Quote Start ---  originally posted by weizbox@Aug 26 2005, 02:34 PM for the application that im going to be using it for, it would have it be counting pulse width, height, and frequency, so i wouldnt need to be sending a stream of this data over the ethernet, just a numbers after it has been sorted out on the fpga side.  --- Quote End ---   Wow. I hope you're not trying to do the pulse width/frequency/etc. stuff in software, because that's way more than Linux (or even a no-OS app) could handle.  That said, this is where Nios shines: the ease of creating custom peripherals. You're going to have to look at your algorithm and split it into "fast tasks" (which need to keep up with the sample rate) and "slow tasks" (which don't). Edge detection/windowing/filtering are examples of fast tasks, and sending packets on Ethernet is a slow task.  Fast tasks will need to be done in hardware on the FPGA, then their results will be passed on to the Nios system (via an Avalon bus interface) where the slow stuff will get done.  If you need to do any signal processing, it looks like you're going to want to use a Stratix II. You might want to look at Altera's DSP Builder evaluation package (which also supports Nios II). I think it's what you're looking for, or at least in the ballpark.    --- Quote Start ---  originally posted by weizbox@Aug 26 2005, 02:34 PM thanks for clearing up the fpga / linux stuff, but i still feel lost on how its all setup on this board and whats runnning and where, etc. but ill check into it a bit more later on, certainly have enough docs on it.  --- Quote End ---   Let me see if I can help clear this up...  It's like the network stack; it's a layer cake.  The bottom layer is the physical hardware. Altera FPGA, ADC, Flash, RAM, etc. live here.  Firmware is designed in Verilog or VHDL. Things like state machines, combinational and registered logic, etc. This gets turned into a bit pattern that is used to configure the FPGA so it acts like the custom firmware says.  One day, someone realized that there were so many gates/registers/RAM bits available in FPGAs that you could design a CPU entirely in firmware. As far as the FPGA is concerned, it's a lot of flip flops and gates, but to us humans, it's a CPU.  Once you have a CPU and hook up memory to it, you have a computer. You can write programs for this and run them just like any other PC, albeit with entirely different capabilities.  This leads to confusion since there are now two different types of "stored programs"; the FPGA configuration bit pattern, and the CPU's stored program. I refer to the former as "firmware" and the latter as "software", but this is far from a universal standard. Be careful.  Once you have CPUs that can run programs, you can write programs that are operating systems, upon which other programs may be run. The cake is getting rather tall, isn't it?  So now we have a system where you can have custom hardware as well as software. It's very flexible, yet more work since there is more design effort on the part of the end user. Enter SOPC Builder, which simplifies a lot of this by taking care of the bus architecture, address decoding, timing, interrupts, multiple bus masters, etc. for you, and brings the workload down to a more sane level.  The ultimate price for this flwxibility is in speed and power consumption. On a Cyclone, you should expect to get a CPU clock speed between 50-100 MHz. (You'll have to be really careful to get 100 MHz.) On a Stratix, I think you can add about 50 MHz to that. Compare to modern DSPs that generally run in the 200 MHz to 1.0 GHz range. Regarding power consumption, the Nios II has no sleep modes nor any way to enable/disable the clock tree to parts of the circuit, so you'll be running "full power" at all times.  Hope this clears some of it up...?

[Altera_Forum]

Thanks Mike! 

That did make things a lot more clear, and as well thats pretty much was I was thinking how it all worked out, but without knowing for sure, it still seemed cloudy. Unfortunetly I dont think I can use this for the initial application I thought I would be able to at first, but it seems like it could be a good way to do some other applications that Im working with. As far as using it for a DSP type setup, this seems too limited for now atleast, possibly later once things get developed moreso.  Now off to work on a more suitable project, getting gui running on it. This should be fun http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/tongue.gif   Thanks again, Mark

[Altera_Forum]

Hi Scott, 

 I too have just purchased a Nios II Evaluation Kit and am trying to figure out how to rebuild uCLinux, Ethernet MAC, and SDRAM controller. The tutorials that came with the kit speak primarily of a "Development" kit. I also want to write a very simple udp application to send packets out of the Ethernet interface but the filesystem appears to be set up as a ramdisk. I.e. whatever I do, I lose when I reboot. Finally, the Linux won&#39;t boot up unless I plug the USB cable into it and launch a console session.   Do you have any advice on where I can go to find some tutorials / information on how all this works?!  Thanks,  Wade       --- Quote Start ---  originally posted by smcnutt@Aug 25 2005, 05:48 PM hi mark,  > is it possible to run the uclinux distro on it,  yes.  > and as well have stand-alone fpga programs running as well?  i&#39;m not sure what you mean by "stand-alone fpga programs" ... but here goes:  -yes, you can write your own applications that run under uclinux. -yes, you can write your own applications that use the hal (no linux). -no, you can&#39;t run them at the same time.  > an example would be me running an adc program  ... snip ... > and then in turn, output it via ethernet.  yes, this is where uclinux and nios ii are a great match. you can do this with a simple device driver and a simple application. you could even setup the web server to monitor data via a browser.  regards, --scott <div align='right'><{post_snapback}> (index.php?act=findpost&pid=9277)  --- quote end ---    --- Quote End ---  

[Altera_Forum]

Hi Wade, 

 > Linux won&#39;t boot up unless I plug the USB cable into it and launch a console > session.   Use a UART as the console ... then you won&#39;t have to deal with this.  > but the filesystem appears to be set up as a ramdisk. I.e. whatever I do, > I lose when I reboot.  Add JFFS2 support. To keep things simple, you can just boot from ramdisk, then mount a small JFFS2 filesystem for the stuff you want to be persistent. Just erase the partition prior to the first mount ... then you can add whatever you want (e.g. use a the ftp client to pull your files onto the JFFS2 mount).  > Do you have any advice on where I can go to find some tutorials / information > on how all this works?!  That depends on what you&#39;re referring to:  For the kernel in general: Start with the Microtronix Tutorial/Guides. Try: http://www.uclinux.org/ (http://www.uclinux.org/) Use the force: read the source.  For everything else: This forum -- you&#39;ll probably get the most help if you break up your work into small chunks & knock them out one-by-one, asking specific questions along the way. As long as your focus is specific enough, you&#39;re likely to attract the attention of an expert ... or at least someone that has already suffered through the same/similar issues ;-)  You might want to consider the following:  1. Get the kernel squared away using a UART console.  2. Get ftp client working -- it&#39;ll let you download quickly so you can have more fun playing with the stuff you _want_ to play with -- rather than fussing with things that you really don&#39;t care about.  3. Fuss with JFFS2/MTD after you decide you can&#39;t live without it.  Regards, --Scott