NIOS II/F With No JTAG

[Altera_Forum]

Hi all, 

 I have a NIOS II/F design which has level 2 debug with JTAG UART.  We want to remove it for various reasons now our production devices can load its own code from ROM.  However, if I cange the debug level to 'no debug' in SOPC builder I get the error   "cpu: Unknown Break Location CPU/JTAG_DEBUG_MODULE"  The problem is I can't change that location in the 'more CPU settings' tab, so I cant clear the error and generate the design!  Any ideas on how to remove the JTAG uart?  [I'm using Quartus 6 and SOPC builder 6 Build 178]  TIA  Tom

[Altera_Forum]

I have the same problem, I have a Nios processor and DDR interface inside a EP2C8Q208 chip and I would like to remove all unnecessary stuff to be able to speed up the processor to >85MHz to make it the same as the DDR clock. 

Another thing is that the jtag_debug_module consumes two M4K blocks that I could use for processor cache.

[Altera_Forum]

there is a solution in the Nios errata, just remove the cpu and add a new without the debugger 

http://www.altera.com/literature/es/es_nios2eds_60.pdf (http://www.altera.com/literature/es/es_nios2eds_60.pdf)

[Altera_Forum]

Excellent http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif Thanks for the info!