Nios 3.2 and flash read problems

[Altera_Forum]

I am using the Nios 3.2 cpu in a Cyclone device. I am also using the Spansion AM29LV065MU-112REI flash since I could not purchase the AMD flash used on the Altera Cyclone eval. board.  

 Using Germs / nios-run, I seem to be always able to program the flash without problems but am having great difficulty reading the flash at specific addresses. For example, if I use "srec2flash" to create a .flash file at base address 0x0 (the base address of my flash in my system) the code will not run but if I create the file to load at 0x2000, the code will copy to my RAM and run fine. The same appears to be true at other addresses within the flash such as 0x200000 vs. 0x202000. After trying to run the code from 0x0, I examine the contents of my RAM and it seems that the copier loop is at least running, even though it might not be copying all of the program code correctly. (I also cannot run the code directly from flash either) If, however, I run the .flash program from, say, 0x2000, the code copies and runs perfectly either when started from flash or from my RAM, after running it once from flash. When I use nios-run to copy the code directly to RAM, it runs perfectly every time.  I think that I may have to modify the flash module but cannot locate it in the design directories. I also tried to add and subtract wait states in the .PTF file. The read access time of my flash is 110 nS and my system clock frequency is 25 mHz, at present although I may change it to 50 mHz. Getting back to the wait states, the Avalon bus manual indicates that the parameters "Read_Wait_States" and "Write_Wait_States" are integer values (e.g. "1", "2", etc) in the .PTF file but, in my .PTF, these values are specified in mHz. At any rate, I could not influence the behavior of this problem in any way by specifying read wait states between values of 0 and 240 mHz (in integer multiples of my system clock frequency, of course)  Also, I am using the flash to store my FPGA .hexout file at 0x600000 and am using a CPLD to configure my FPGA from the flash. The FPGA always configures without errors; the CPLD is addressing the flash at about 1/7 system clock frequency. However, if I load code to 0x600000 and try to execute it, I have the same problem, it will not copy and run correctly, If I load it at 0x602000, it will.  Any ideas???