Omitting dcache AND icache in f-core

[Altera_Forum]

Hello, 

 is it possible to omit both, dcache and icache from f-core CPU (in NiosII v1.1)?  Since it is possible to generate a f-core CPU without dcache by setting the 'cache_omit_dcache' flag in the ptf-file to "1", I wonder why it does not work for the icache as well.  When I use the 'cache_omit_icache' flag SOPC builder comes up with an error ("instruction master: I-cache must be present - Error: Generator program for module 'cpu' did NOT run successfully.").  For my project f-core capabilities and speed are essential. In addition I have to keep memory usage as low as possible. Are there any speed penalities as consequence of omitting the caches (only on-chip memory is present)?  jackie

[Altera_Forum]

If your algorithm has tight loops then you will take a performance hit removing the instruction cache (not that you can with the f core anyway though). You can't turn off the icache in the f-core due to the design of the core (without an instruction cache you might as well use the e-core). The main purpose of an icache is so that if you have repetative structure in your code (a loop for example), then you don't need to be constantly going out on the avalon bus to read the next instruction if you can keep that information cached. The only case (well one of the only cases) where cache does not help you is if you have a lot of code to be executed within a repetative structure (the code inside the loop is larger then the size of your cache). That's a simplistic view of it (there's a bit more to it than that). 

 Since you are worried about onchip resources, I recommend picking your memory wisely then (if you have MRAM available use it when you can). Also don't forget to use compiler optimizations in the Nios II IDE to reduce the memory footprint.

[Altera_Forum]

Thank you for your information BadOmen! 

 To sort things out, I completely agree with your explanation of the main purpose of caches. However, what happens when cache and memory operate at the same speed? In my design only on-chip memory - every M4k block not used by other entities - is present. As I understand the documentation of Avalon bus a read transfer may be issued in each cycle, no latency. So the complete transfer is finished within one cylce. I do not understand, why fetching from cache should be faster than that.  jackie

[Altera_Forum]

Hi Jackie, 

 the Avalon-bus can issue a transfer every cycle, however there is some latency (pipelining) for every transfer. This is necessary to achieve the fmax, I think. As soon as you have a branch, you get this latency penalty from the Avalon-bus (in addition to CPU-internal pipelining). I think this is the main reason for instruction cache. Pure speculation: As the instruction cache cannot be disabled, I suppose the nios2-core itself is no longer latency-aware as the nios1 was, only together with the i-cache.  But I understand your toughts, you could also think it in the other way with using all the available M4Ks as cache and store the complete programm in the cache. But this is not possible, I think. If you are using the EPCS or another external flash, a solution could be to build such a large cache and execute the code from the EPCS or external flash. This would be very slow until everything is in the cache, but after that there would never be cache misses because the cache is large enough.  BTW: Beside the Nios being generally pretty quick, there are some extra-cycles here and there that you would not have expected from the documentation. Especially loads from memory without data-cache are really slow. So if you really need performance, try to keep your things in the registers or use the data-cache. However, most of my observations were with the s-core. Without data-cache you may be better of with the s-core anyway.  Thomas

[Altera_Forum]

Jackie, there will be several new features in the Nios II 1.2 release that might meet your requirements. 

This release should be available early this summer (we are finishing up the development and testing right now). Unfortunately I can't give you details about what is coming. How's that for a teaser?

[Altera_Forum]

Thank you all for your comments. 

 I am looking forward to the new features of NiosII v1.2.  jackie