PLL of LVDS Clocking the Whole Design - SOPC Custom Component

[Altera_Forum]

Hi, 

 I am designing custom SOPC components for my board. One of those components is a controller for a fast ADC (2 x 1.6 GHz). Inside this component I have an ALTLVDS. So, I have the following clock design:  1. I have an ADC_CLK input @ 400 MHz at top level; 2. I route this ADC_CLK to the custom SOPC ADC controller via a conduit interface; 3. Inside the custom ADC controller I feed the LVDS with the ADC_CLK which (the LVDS, of course, has its own PLL). The PLL in the LVDS gives my CLK_LVDS @ 100 MHz; 4. I route this CLK_LVDS out via a conduit interface to the top level; 5. At the top level, I use CLK_LVDS to clock the whole design.  So the design works fine. I can even change the main frequency up and down a little bit. The problem is with fmax and the timing analysis. I have the feeling that the router and/or time quest don't do something right. I set one clock for timequest and this is the top level ADC_CLK @ 400 MHz. The problem is that it doesn't fit and gives me an fmax of approx. 105 MHz (should be 400 MHz as the 400MHz are only used for the LVDS).  So what am I doing wrong? How am I supposed to manually constrain all this? Or, shall I use some more elaborate SOPC approach?  Your opinions would be highly appreciated - I don't have much experience as a hardware designer.  Thanks,  -- Alex

[Altera_Forum]

Your design looks OK. 

 Top of my head: You need to set a constraint for each clock at least. But you can just use the "derive_pll_clocks" command to set constraints for each of the PLL generated clocks.  A 400 MHz clock input is only supported if it's LVDS and it's the the maximum limit, at least for some devices. Is your ADC_CLK a LVDS signal? Does your device support a 400 MHz clock input?  More than that, you'll need to check the paths that are failing to meet the constraints.

[Altera_Forum]

Your advice is much appreciated. What you told me to do ("derive_pll_clocks"), saved me, probably, a whole day of reading the TimeQuest manual and the latter is not very interesting anyway. 

 So, I solved my fmax issues. I had to cheat a little bit though.  My FPGA is grade 7. The LVDS input sampling rate is 706 MHz (I told you 400 in my previous email because I set it so to fool the timing analysis).  When I set 706 Mhz for the LVDS (this results in 88.25 MHz for the rest of the design), I get an error that the maximum data rate for the LVDS is 640 Mhz. So, I go to the assignments and set a different FPGA device (grade 6, everything else is the same).  At this point everything fits smoothly. I even get some extra fmax.  So, I am overclocking the LVDS part with 10% and cheating about the FPGA speed grade. Am I doing something very bad and going to rot in hell?

[Altera_Forum]

Yes, you're doing something very bad. 

There's no way for you to know if the design will actually work reliably or not. It may work fine for a given FPGA at a given temperature and voltage and not work on the next one.  Note 1: there are performance differences between C7, I7 and A7 grades. Make sure you're not mixing them up.  Note 2: So, you have a 706 Mbit/s input rate. What _clocks_ are you actually using?  Note 3: After you sorted that out, remember to take a look at this document: http://www.alteraforum.com/forum/attachment.php?attachmentid=201&d=1191905857

[Altera_Forum]

--- Quote Start ---  Yes, you're doing something very bad. There's no way for you to know if the design will actually work reliably or not. It may work fine for a given FPGA at a given temperature and voltage and not work on the next one.  Note 1: there are performance differences between C7, I7 and A7 grades. Make sure you're not mixing them up.   --- Quote End ---   It is a C7 (EP2C70F672C7).   --- Quote Start ---  Note 2: So, you have a 706 Mbit/s input rate. What _clocks_ are you actually using?   --- Quote End ---   The LVDS input clock (ADC_CLK) is 353 MHz (can be programmed up to 360 MHz via an external PLL). The C7 device seems to support up to 320 MHz. The PLL in the LVDS divides this by 4, so CLK_LVDS (this is the NIOS clock) is 88.25 MHz.   --- Quote Start ---   Note 3: After you sorted that out, remember to take a look at this document: (removed link because of bad carma)   --- Quote End ---   Thanks, I'm launching a Windows client so I can open it.

[Altera_Forum]

OK, forgot to mention that this is a Cyclone II, so it has an GPIO LVDS. The above document is still worth reading, though, because then I understand LVDS timing better.

[Altera_Forum]

What do you mean by GPIO LVDS? 

Are you using some kind of development board?  Anyway.. if you already have the hardware up and running, try it. Otherwise, I'd replace the FPGA with a faster part.

[Altera_Forum]

--- Quote Start ---  What do you mean by GPIO LVDS?  --- Quote End ---    It seems like (from the document you referred to), that Altera Startix have an LVDS implemented in Silicone. The Cyclone series, on the other hand, use "soft" LVDS. Clearly, this makes a difference in the timing analysis.    --- Quote Start ---  Are you using some kind of development board?  --- Quote End ---    Yeah. This is custom design software radio-like stuff. Dual 8-bit ADC (2 x 1.4 MHz), cheap FPGA (Cyclone II).    --- Quote Start ---  Anyway.. if you already have the hardware up and running, try it. Otherwise, I'd replace the FPGA with a faster part.  --- Quote End ---    Thanks, I have already spoken to the guy who has designed the board and he told me that he is aware, and used the C7 only because C6 was not available at this time. Next revision of the board (if one is ever to be produced) will be with C6 and some other niceties.  Anyway, it seems to work, this is dev only, and I'm quite OK designing for C6 and running on C7 with 10% out of the envelope.