The question about Configuration device.

[Altera_Forum]

The Altera NiosII Dev.Board uses the EPM7128 as the configuration download device, but Microtronix Cyclone Dev.Board has not. So I want to know how the NiosII runs the code stored in the flash on Microtronix Board. 

 In addition, when I make a nios2 system(nios2+uart+timer+sdram+flash+Opencores 10/100 Ethernet MAC), it is always warning "cpu: The reset address point to volatile memory. Execution of undefined code may occur upon reset.". I don't know what's wrong, but I have set the "Reset Address as flash" and "Exception Address as sdram". Then I edit my nios2 with getting rid of the jtag_debug_module, and add the legacy component "On Chip Memory", set it as Rom with Germs Monitor, and also re-edit the reset address with On Chip Memory. Finally, no warning appears. I don't know what's wrong, can someone tell me?  Thank you.

[Altera_Forum]

--- Quote Start ---  originally posted by liangyi+dec 28 2004, 09:38 am--><div class='quotetop'>quote (liangyi @ dec 28 2004, 09:38 am)</div>  --- quote start ---  the altera niosii dev.board uses the epm7128 as the configuration download device, but microtronix cyclone dev.board has not. so i want to know how the niosii runs the code stored in the flash on microtronix board.[/b]  --- quote end ---   hello liangyi,  the following is taken from the data sheet of the microtronix cyclone development kit:  <!--quotebegin-microtronix in addition, when i make a nios2 system(nios2+uart+timer+sdram+flash+opencores 10/100 ethernet mac), it is always warning "cpu: the reset address point to volatile memory. execution of undefined code may occur upon reset.". i don&#39;t know what&#39;s wrong, but i have set the "reset address as flash" and "exception address as sdram".  --- Quote End ---    In my design the Reset Address is pointing to “ext_flash†and Exception Address is pointing to “sdramâ€. The base of ext_flash is 0x0 and is locked. Did you locked the base address?    Bye, niosIIuser

[Altera_Forum]

Hello,  

 The first question I mean that EPM7128 is used as flash code download device(just store OS or App code in flash), not used as the configuration of FPGA(don&#39;t store .pof file).   Second, You say "In my design the Reset Address is pointing to “ext_flash†and Exception Address is pointing to “sdramâ€. The base of ext_flash is 0x0 and is locked. Did you locked the base address?" Yes, I did. But the same. So I think it maybe the wrong of the component(microtronix cyclone dev board flash). I have a test and change the Mtx gived flash component to Flash Memory(Common flash Interface) of the Altera SOPC Build provided. I set Address Width and Data Width(but I don&#39;t know how to set the Timing). This time no warning occurs. Why? http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif  This do not appear in SOPC Builder 2.7, but occurs in SOPC Builder 4.1.  Thank you.

[Altera_Forum]

Hello LiangYi, 

 Altera Nios II Development Board: The CPLD (EPM7128) is used reset handling and for configuring the FPGA. The configuration data is stored in the upper space of the flash and will be read out from the CPLD during start up. The application code for the Nios II is stored in the lower space of the flash (address 0x0).  Microtronix Cyclone Development Board: The configuration data for the FPGA is stored in the serial EEPROM (EPCS4). The FPGA will be configured automatically during start up. The flash is only used for storing the application code for the Nios II. (I don’t know details about the DK from Microtronix, all I know is the information from the data sheet).  If you have more problems with your Microtronix DK I think you should contact Microtronix directly.  I hope the information will help you a little bit.   Bye, niosIIuser