Hi all,
I have follwoing problem with the SoPC UART component.
When I create this component inside the SoPC Builder (NIOS was created too) and after I generate the whole system, everthing works.
When switch to Quartus and I try to synthesize my nios system I get following error message
Error (10232): Verilog HDL error at Altera_UP_RS232_In_Deserializer.v(148): index 10 cannot fall outside the declared range [9:0] for vector "data_in_shift_reg"
The SoPC was build in VHDL. What I make wrong, any ideas?
Thanks
ThomasM
