Vitesse PHY Register controlling Via MDIO using Nios Processor

[Altera_Forum]

Hiii, 

 Anybody know how Nios II can control VSC8486 – Vitesse Phy via MDIO ie how to write and read via MDIO to Vitesse External phy ??  pls share your experience  asickrishna

[Altera_Forum]

MDIO is a standard two-wire interface. A MDIO core is provided within SOPC-builder/Qsys embedded IP library, so you only need to instantiate it into your system. Then you use the HAL driver to access VSC8486 registers.

[Altera_Forum]

I have created MDIO core in Qsys and i want to know how we can write external Phy registers via MDIO ie Nios Application for MDIO read and Write to External Phy.

[Altera_Forum]

You must use simple IORD/IOWR calls to the MDIO core registers. 

Take a look to the embedded IP user guide:  http://www.altera.com/literature/ug/ug_embedded_ip.pdf and consider this errata, which also explains the phy register access procedure:  http://www.altera.com/support/kdb/solutions/rd10052010_44.html

[Altera_Forum]

can you please explain or share the c application that you have did for Nios MDIO interface ? 

 i want to know how we can read and write and we need to set some address initially .. can you share those details  i got some picee of code  pls see alt_u32 t2=0;  IOWR_ALTERA_TSEMAC_MDIO_ADDR1(TRIPLE_SPEED_ETHERNE T_0_BASE, 0); // PHY and other board peripheral initialization IOWR_ALTERA_TSEMAC_MDIO_ADDR0(TRIPLE_SPEED_ETHERNE T_0_BASE, PHY); do { // Control Register .15 = 1 - Reset IOWR_ALTERA_TSEMAC_MDIO(TRIPLE_SPEED_ETHERNET_0_BA SE, 0, 0, 0x8000); Delay(0xFFFF); // (.13=0, .6=1) - 1000 Mbps, .12=1 - Enable Auto-Negatiation, IOWR_ALTERA_TSEMAC_MDIO(TRIPLE_SPEED_ETHERNET_0_BA SE, 0, 0, 0x1040); Delay(0xFFFF); // read Control Register t2 = IORD_ALTERA_TSEMAC_MDIO(TRIPLE_SPEED_ETHERNET_0_BA SE, 0, 1); Delay(0xFFFF); // Control Register .15 = 1 - Reset IOWR_ALTERA_TSEMAC_MDIO(TRIPLE_SPEED_ETHERNET_0_BA SE, 0, 0, t2 | 0x8000); Delay(0xFFFF); // read Staus Register t2 = IORD_ALTERA_TSEMAC_MDIO(TRIPLE_SPEED_ETHERNET_0_BA SE, 0, 1); alt_printf("Reg 1 : %x\n",t2); //check Link if( (t2&0x0004)==0 ) { // Control Register .15 = 1 - Reset IOWR_ALTERA_TSEMAC_MDIO(TRIPLE_SPEED_ETHERNET_0_BA SE, 0, 0, t2 | 0x8000); Delay(0xFFFF); } // .15=1 - Copper, (.3:.0)='0100' - SGMII without Clock with SGMII Auto-Neg to copper IOWR_ALTERA_TSEMAC_MDIO(TRIPLE_SPEED_ETHERNET_0_BA SE, 0, 27, 0x8004); Delay(0xFFFF); // read Staus Register t2 = IORD_ALTERA_TSEMAC_MDIO(TRIPLE_SPEED_ETHERNET_0_BA SE, 0, 1); alt_printf("Reg 1 : %x\n",t2); } while( (t2&0x0004)==0 );

[Altera_Forum]

The code you show here is supposed to be used with the Altera Triple Speed ethernet core, which only supports clause 22 MDIO. From what I see, your PHY is a 10GbE transceiver and as such probably requires a clause 45 MDIO, which the module presented by Cris72 supports. 

The embedded IP user guide presents the register on page 14-4. Use IOWR(your_base_address,0x84,x) with x containing the correct values for MDIO_DEVAD, MDIO_PRTAD and MDIO_REGAD and then you can either read a PHY register with IORD(your_base_address,0x80) or write with IOWR(your_base_address,0x80,x). Of course you must replace your_base_address with the constant defining the MDIO core base address.

[Altera_Forum]

MDIO Read and write via NIOS II 

 # include <stdio.h># include <system.h># include <altera_avalon_pio_regs.h># include <io.h># include "mdio_cmm.h"  int main() {  alt_u32 data32;  printf("Hello from Nios II!\n");   IOWR_ALTERA_AVALON_PIO_DATA (PIO_0_BASE, 0);  delay(50);  IOWR_ALTERA_AVALON_PIO_DATA (PIO_0_BASE, 1);  // writing  IOWR_32DIRECT(ETH_MDIO_0_BASE,0x84,0x80000001);   IOWR_32DIRECT(ETH_MDIO_0_BASE,0x80,0x0000b55d);  //Reading  delay(50);  IOWR_32DIRECT(ETH_MDIO_0_BASE,0x84,0x80000001);  data32 = IORD_32DIRECT(ETH_MDIO_0_BASE, 0x80);   printf ("%x",(int)data32);    return 0; } void delay(int in) {  int count;  for(count = 0; count < in; count++);  return; }

[Altera_Forum]

--- Quote Start ---  MDIO Read and write via NIOS II  # include <stdio.h># include <system.h># include <altera_avalon_pio_regs.h># include <io.h># include "mdio_cmm.h"  int main() {  alt_u32 data32;  printf("Hello from Nios II!\n");   IOWR_ALTERA_AVALON_PIO_DATA (PIO_0_BASE, 0);  delay(50);  IOWR_ALTERA_AVALON_PIO_DATA (PIO_0_BASE, 1);  // writing  IOWR_32DIRECT(ETH_MDIO_0_BASE,0x84,0x80000001);   IOWR_32DIRECT(ETH_MDIO_0_BASE,0x80,0x0000b55d);  //Reading  delay(50);  IOWR_32DIRECT(ETH_MDIO_0_BASE,0x84,0x80000001);  data32 = IORD_32DIRECT(ETH_MDIO_0_BASE, 0x80);   printf ("%x",(int)data32);    return 0; } void delay(int in) {  int count;  for(count = 0; count < in; count++);  return; }  --- Quote End ---    Is anybody worked Vitesse PHY ? i am having one doubt   Our design has p and n transceivers lines of VITESSE chip connected to SFP+. But the lines are connected in criss cross way i..e P transceiver channel of VITESSE chip is connected to N transceiver channel of SFP+. The only way we figured out to solve this issue is to reconfigure VITESSE chip to change the polarity within the VITESSE chip. This we are doing with MDIO interface. We figured out a particular register value 0x8000 doing this operation of swapping the channels. We are doing this successfully but we see that there is no link going up in SFP+.  My understanding, the only way to confirm the lines polarity swapped is by observing the link getting up (which we are not seeing now).