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What's the general way to incorporate handwritten module with TSE ethernet?

Altera_Forum
Honored Contributor II
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Suppose we have handwritten IP module that continuously reads data from ADC, processes it and writes to some on-chip fifo. Now we want to send those data via Ethernet. I got impression the common way for doing this is to build SOC in SOPC builder with NIOS, TSE, SGDMAs, DDR, descriptor memory, packet memory etc. and run ucos with Interniche stack to get ethernet. I am a newbie in NIOS embedded programming and it is not clear for me how to program software in order to move data from my module to TSE. If I instantiate my module in SOPC as a streaming source, can I somehow directly connect it to TSE transmit sink? Or I have to go through buffer packet memory as I saw in examples? Do I need to write driver for my module for data transfers? Lots of questions, but the general one is how to interface handwritten module with SOPC\NIOS IDE and move data fast from it to TSE in software\hardware?

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Altera_Forum
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Hello, 

 

Depending the protocol you want to use via Ethernet, you don't have to use an TCP/IP stack with an OS running... 

 

I've done some design using the TSE in "stand alone mode" in order to transfert data using UDP protocol. You just have to instanciate it, write some logic interface between the TSE and your IP/FIFO and your're done. The only thing anoying is computing CRCs. 

 

However, I you prefer/need to use a NIOS/OS/DDR I'm sorry I can't help you :) 

 

Regards, 

Franck.
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Altera_Forum
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--- Quote Start ---  

Hello, 

 

Depending the protocol you want to use via Ethernet, you don't have to use an TCP/IP stack with an OS running... 

 

I've done some design using the TSE in "stand alone mode" in order to transfert data using UDP protocol. You just have to instanciate it, write some logic interface between the TSE and your IP/FIFO and your're done. The only thing anoying is computing CRCs. 

 

However, I you prefer/need to use a NIOS/OS/DDR I'm sorry I can't help you :) 

 

Regards, 

Franck. 

--- Quote End ---  

 

 

Could you explain more about that logic interface?
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Altera_Forum
Honored Contributor II
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Hello, 

 

The output protocol of the TSE is very simple. You have a "start of packet", "end of packet", data, and data valid and some optional and informative signals.  

 

Knowing this, you can send receive frame easely. Don't forget to configure the TSE via the avalon interface. 

 

Regards, 

Franck.
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Altera_Forum
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OK, I implemented gigabit ethernet on CycloneIII 3C120 development board. I used ucos, TSE MAC, interniche and custom peripheral with avalon slave interface which exposes conduit ports to my tx\rx FIFOs outside SOPC system. Doing PIO register reads to my FIFO I am able to get ~20Mbps tx speed, while benchmarking ethernet speed without PIO accesses I can get at least 40Mbps. So, it is clear that my speed now is limited by those slow IORDs. I am thinking about some faster interface like DMA.  

Did anybody make such system with fast data transfers from custom peripheral to TCP send()?
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Altera_Forum
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dagofff, the fastest solution is that was proposed by crevars. I'm using also a custom hardware for UDP generation, the transmission to the TSE Mac is done by SGDMA. The custom hardware has a Avalon Slave port which is connectet to the m_read port of the sgdma_tx. My design is based on TSE_SGDMA example. You can find that i.e. in C:\altera\72\nios2eds\examples\vhdl\niosII_stratixII_2s60_RoHS. 

 

With a software based solution is a speed between ~30MBits/s and ~145MBits/s (according AN440, page 18) possible. The max speed I use in my hardware solution is about 640 MBit/s. 

 

The best way may be you try to adapt the tse_optimized design according AN440. If the bandwith is to small than you must implement a hardware protocol engine. 

 

here you can download AN440 and design files: 

http://www.altera.com/literature/lit-an.jsp (http://www.altera.com/literature/lit-an.jsp

 

Jens
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

Hello, 

 

The output protocol of the TSE is very simple. You have a "start of packet", "end of packet", data, and data valid and some optional and informative signals.  

 

Knowing this, you can send receive frame easely. Don't forget to configure the TSE via the avalon interface. 

 

Regards, 

Franck. 

--- Quote End ---  

 

 

Hi, 

 

I was trying to do the same and wrote simple logic that processes raw Ethernet frames. However, I couldn't manage to make the hardware run successfully. I am doing the reset correct I think, but I haven't done any initialization. Since I don't use Nios, I wanted to write some Verilog code for issuing commands to the Avalon MM Slave interface of the TSE MAC, but that was unsuccessful until now. Could you tell me how did you configure the TSE registers through the avalon interface? In particular, I am having difficulties understanding the addressing. Here is my code, I was just trying to turn the leds on and off if I read TX_EN and RX_EN to be 1, but they are always 0: 

case (reg_point) 

 

one: begin ctrl_read = 1'b1;  

ctrl_address[7:0] = 8'h02; 

next_reg_point = two; 

end  

two: begin temp_ctrl_readdata[31:0] = control_readdata[31:0]; 

if (temp_ctrl_readdata[0] == 1'b1) 

begin stat = 1'b0;  

end 

next_reg_point = three;  

end  

three: begin ctrl_write = 1'b1;  

ctrl_address[7:0] = 8'h02; 

ctrl_writedata[31:0] = 32'h00002211; 

if (ctrl_readdata[0] == 1'b1) 

begin stat = 1'b0;  

end 

next_reg_point = four; 

end 

four: begin ctrl_read = 1'b1;  

ctrl_address[7:0] = 8'h02; 

next_reg_point = five; 

end 

five: begin temp_ctrl_readdata[31:0] = control_readdata[31:0]; 

if (temp_ctrl_readdata[0] == 1'b1) 

begin stat = 1'b0;  

end 

next_reg_point = six; 

end  

six: begin if (ctrl_readdata[1:0] == 2'b11) 

begin led6 = 1'b0; 

stat = 1'b0;  

end 

next_reg_point = seven; 

end 

 

seven: begin if (ctrl_readdata[1:0] == 2'b11) 

begin led6 = 1'b0; 

stat = 1'b0;  

next_reg_point = seven; 

end 

 

 

 

 

This is the comb logic. In the sequential logic block I do the following:  

state <= next_state;  

reg_point <= next_reg_point; 

 

if (state == idle && ( (next_reg_point == three) || (next_reg_point == six))) 

ctrl_readdata <= temp_ctrl_readdata;
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Altera_Forum
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Hi vaka, 

 

which Hardware you are using? If there is an ethernet example for it then the best way will be to start with that. 

If you have an ethernet connection running the MAC and PHY are properly initialized, you can read the register settings. 

 

for the TSE Registers 

ulRegValue = IORD_32DIRECT( TSE_MAC_BASE, REG_OFFSET ); 

 

for the PHY Registers via MDIO Interface 

ulRegValue = IORD_32DIRECT( TSE_MAC_BASE + 0x200, REG_OFFSET ); 

 

If you will use the Interniche TCP/IP stack you can look at the function tse_mac_init(int iface) in ins_tse_mac.c for initialization of MAC and PHY. 

(in \altera\14.1\ip\altera\ethernet\altera_eth_tse\src\software\lib\UCOSII\src\iniche\) 

 

Jens
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Altera_Forum
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--- Quote Start ---  

Hi vaka, 

 

which Hardware you are using? If there is an ethernet example for it then the best way will be to start with that. 

If you have an ethernet connection running the MAC and PHY are properly initialized, you can read the register settings. 

 

for the TSE Registers 

ulRegValue = IORD_32DIRECT( TSE_MAC_BASE, REG_OFFSET ); 

 

for the PHY Registers via MDIO Interface 

ulRegValue = IORD_32DIRECT( TSE_MAC_BASE + 0x200, REG_OFFSET ); 

 

If you will use the Interniche TCP/IP stack you can look at the function tse_mac_init(int iface) in ins_tse_mac.c for initialization of MAC and PHY. 

(in \altera\14.1\ip\altera\ethernet\altera_eth_tse\src\software\lib\UCOSII\src\iniche\) 

 

Jens 

--- Quote End ---  

 

 

Hi Jens, 

 

I am using Stratix V SI transceiver development kit board with instantiated TSE without Qsys and without Nios. I will do raw Ethernet, so no need for TCP/IP. I have simulated the behaviour of the handwritten logic above MAC and it works fine. So, the Avalon ST interface is finished, however I am having problems receiving data from the PC and I assume the it is some kind of problem with the initialization. Is it mandatory to do the initialization, what happens if I don't configure the registers? I am sending broadcast frames from the PC, so those should pass anyway no matter the MAC address of my FPGA. What else could be going wrong with the MAC and PHY that stops me from receiving anything after the MAC?
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Altera_Forum
Honored Contributor II
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Hi vaka, 

 

The initialization of MAC/Phy in our case is done by the TSE MAC driver software.  

After init we check the bit 5 of copper status register of the Marvell 88E1111. If Auto-Negotiation process is completed we can use the interface. 

Then it's possible to get a ping reply from the hardware.  

 

Is the Link between your PC and the hardware established? (orange LED at 1000GBit) 

Do you have provided all necessary signals to/from the 88E1111? (gtx_clk, tx_en, tx_d, rx_dv, rx_d, mdio, mdc, reset_n) 

If you don't able to use a TCP/IP stack refer AN647. There is a description of a reference design just with Ethernet packet generator and monitor. 

Control and initialization of MAC and PHY is done by system console with some tcl-scripts. 

Look in the ref design subdirectory sc_tcl for tse_marvel_phy.tcl and tse_mac_config.tcl 

 

Jens
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Altera_Forum
Honored Contributor II
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Hi,  

Thanks for the reply. I just switched to SGMII instead of RGMII and managed to read out high level on bit 5 for Marvel. In both cases, I could see LED activity, duplex and 1G LED were on, but I assume the clocking is a bit more complex in the RGMII case, so maybe there was some problem there... Also I just figured out that due to the waitrequest signal I was able to read out the correct value only sometimes. When I was actually reading the value the reg_busy is low, so I know that the read out value is the one stored in the register... This explains why a lot of times I was reading out zeros, because I wasn't really reading... Now I will try by just configuring the MAC registers using Verilog and I hope it will work... Thanks anyway
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