Worst slack values are Negative for Removal

[Altera_Forum]

HI , 

 I am trying to run the NIOSII example of led from the nios2 hardware manual.I could generate the nios 2 system.And also integrate it with the Quartus.But when I compile the system in quartus I get the Worst-case Slack values are negative numbers for Removal in Time quest timing Analyser.   But the document says that :  The Worst-case Slack values are positive numbers for Setup, Hold, Recovery and Removal. If any of these values are negative, the design might not operate properly in hardware. To meet timing, adjust Quartus II assignments to optimize fitting, or reduce the oscillator frequency driving the FPGA.  I cant reduce the clock frequency as I using the min freq of 50 Mhz. How to optimise the fitting? I tried to find it but couldnt get it.  Can some one explain what the worst slack values for removal means?   I also have these critical warnings:  Critical Warning: The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.  Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)  Critical Warning: From altera_reserved_tck (Fall) to altera_reserved_tck (Rise) (setup and hold)  Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)  Critical Warning: From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)  Critical Warning: From sopc_clk (Rise) to sopc_clk (Rise) (setup and hold)  Critical Warning: From sopc_clk (Fall) to sopc_clk (Rise) (setup and hold)  Critical Warning: From sopc_clk (Rise) to sopc_clk (Fall) (setup and hold) Critical Warning: The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.  Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)  Critical Warning: From altera_reserved_tck (Fall) to altera_reserved_tck (Rise) (setup and hold)  Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)  Critical Warning: From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)  Critical Warning: From sopc_clk (Rise) to sopc_clk (Rise) (setup and hold)  Critical Warning: From sopc_clk (Fall) to sopc_clk (Rise) (setup and hold)  Critical Warning: From sopc_clk (Rise) to sopc_clk (Fall) (setup and hold) Critical Warning: Timing requirements not met Critical Warning: The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.  Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)  Critical Warning: From altera_reserved_tck (Fall) to altera_reserved_tck (Rise) (setup and hold)  Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)  Critical Warning: From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)  Critical Warning: From sopc_clk (Rise) to sopc_clk (Rise) (setup and hold)  Critical Warning: From sopc_clk (Fall) to sopc_clk (Rise) (setup and hold)  Critical Warning: From sopc_clk (Rise) to sopc_clk (Fall) (setup and hold) Critical Warning: Timing requirements not met Critical Warning: The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.  Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)  Critical Warning: From altera_reserved_tck (Fall) to altera_reserved_tck (Rise) (setup and hold)  Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)  Critical Warning: From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)  Critical Warning: From sopc_clk (Rise) to sopc_clk (Rise) (setup and hold)  Critical Warning: From sopc_clk (Fall) to sopc_clk (Rise) (setup and hold)  Critical Warning: From sopc_clk (Rise) to sopc_clk (Fall) (setup and hold) Critical Warning: Timing requirements not met    :confused:  Regards Sneha

[Altera_Forum]

Well, you can always reduce the frequency by adding a pll in the clock path. 

It might be that just adding a pll already fixes your problem, but if timing already fails at 50MHz, something in your design seems really off.  I usually define every altera_reserved_* as false path, but that might not help you just yet.

[Altera_Forum]

HI , 

 I reduced the clk frequency to 25 Mhz.But still I have the same problem. Earlier I had negative values only in altera reserved clk (worst case slack) and altera reserved clk (Design wide TNS) .  But now at 25 Mhz I get negative values even in sopc clk.  How are these negative values goin to affect the H/W. Can you explain? Its my first demo with Altera and I dont understand it.

[Altera_Forum]

With a .sdc file open, go to the Quartus II --> edit --> insert template. If you look under timequest you should find the JTAG constraints. Those are the ones you are missing and these are the types of failures you can't fix by changing the clock frequency since recovery/removal paths have to do with the reset path and not the data path. For board delays I just eyeball it and overestimate....... although I probably just use 1us for the JTAG logic and call it a day most of the time :)

[Altera_Forum]

Hi, 

 This is the .sdc file I received with the demo. # Update -period with clock period (in nanoseconds) of the clock driving the fpga create_clock -name sopc_clk -period 20 [get_ports PLD_CLOCKINPUT] # Setting LED outputs as false path, since no timing requirement set_false_path -from * -to [get_ports LEDG [*]] # Constraining JTAG interface# TCK port create_clock -name altera_reserved_tck -period 100 [get_ports altera_reserved_tck]# cut all paths to and from tck set_clock_groups -exclusive -group [get_clocks altera_reserved_tck]# constrain the TDI port set_input_delay -clock altera_reserved_tck 20 [get_ports altera_reserved_tdi]# constrain the TMS port set_input_delay -clock altera_reserved_tck 20 [get_ports altera_reserved_tms]# constrain the TDO port# JTAG Signal Constraints constrain the TCK port create_clock -name tck -period __period [get_ports altera_reserved_tck]# Cut all paths to and from tck set_clock_groups -asynchronous -group [get_clocks tck]# Constrain the TDI port set_input_delay -clock tck -clock_fall __tdiBoardDelayValue [get_ports altera_reserved_tdi]# Constrain the TMS port set_input_delay -clock tck -clock_fall __tmsBoardDelayValue [get_ports altera_reserved_tms]# Constrain the TDO port set_output_delay -clock tck -clock_fall __tdoBoardDelayValue [get_ports altera_reserved_tdo]  set_output_delay -clock altera_reserved_tck 20 [get_ports altera_reserved_tdo]  I followed the said proceedure advised by you.  And I inserted a user template with the jtag constrains as  # JTAG Signal Constraints constrain the TCK port create_clock -name tck -period __period 1000[get_ports altera_reserved_tck]# Cut all paths to and from tck set_clock_groups -asynchronous -group 1000[get_clocks tck]# Constrain the TDI port set_input_delay -clock tck -clock_fall __tdiBoardDelayValue 1000[get_ports altera_reserved_tdi]# Constrain the TMS port set_input_delay -clock tck -clock_fall __tmsBoardDelayValue 1000[get_ports altera_reserved_tms]# Constrain the TDO port set_output_delay -clock tck -clock_fall __tdoBoardDelayValue 1000[get_ports altera_reserved_tdo]  Here I set all the timing constraint parameters with jtag in the sdc file.  But still the worst slack value is negative:  altera_reserved_tck 11.428 0.161 43.369 -2.246 29.289 Worst-case Slack 5.911 0.112 3.557 -2.246 9.546  altera_reserved_tck 0.000 0.000 0.000 -2.246 0.000 Design-wide TNS 0 .0 0.0 0.0 -2.246 0.0  There is problem in the fitter design  I am using cyclone 3 development board with EP3C120F780C7   I am newbie with altera Please help?

[Altera_Forum]

Use something like this instead: 

 # JTAG Signal Constraints constrain the TCK port (uncomment the line below if altera_reserved_tck isn't already defined)# create_clock -name tck -period 100 # Cut all paths to and from tck set_clock_groups -asynchronous -group # Constrain the TDI port set_input_delay -clock altera_reserved_tck -clock_fall 1 # Constrain the TMS port set_input_delay -clock altera_reserved_tck -clock_fall 1 # Constrain the TDO port set_output_delay -clock altera_reserved_tck -clock_fall 1

[Altera_Forum]

HI , 

 I modified the constraint file with this : # Update -period with clock period (in nanoseconds) of the clock driving the fpga create_clock -name sopc_clk -period 20 [get_ports PLD_CLOCKINPUT] # Setting LED outputs as false path, since no timing requirement set_false_path -from * -to [get_ports LEDG [*]]  # Constraining JTAG interface# TCK port create_clock -name altera_reserved_tck -period 100 [get_ports altera_reserved_tck]# cut all paths to and from tck set_clock_groups -exclusive -group [get_clocks altera_reserved_tck]# constrain the TDI port set_input_delay -clock altera_reserved_tck 20 [get_ports altera_reserved_tdi]# constrain the TMS port set_input_delay -clock altera_reserved_tck 20 [get_ports altera_reserved_tms]# constrain the TDO port set_output_delay -clock altera_reserved_tck 20 [get_ports altera_reserved_tdo] # JTAG Signal Constraints constrain the TCK port  create_clock -name tck -period 100 [get_ports altera_reserved_tck]# Cut all paths to and from tck set_clock_groups -asynchronous -group [get_clocks altera_reserved_tck]# Constrain the TDI port set_input_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tdi]# Constrain the TMS port set_input_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tms]# Constrain the TDO port set_output_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tdo]  but still the worst slack time for removal is negative.  altera_reserved_tck 0.000 0.000 0.000 -2.347 0.000 Design-wide TNS 0.0 0.0 0.0 -2.347 0.0  altera_reserved_tck 43.109 0.181 42.831 -2.347 29.289 Worst-case Slack 6.011 0.082 3.704 -2.347 9.550  But it says that: # Update -period with clock period (in nanoseconds) of the clock driving the fpga  Should nt we put the value in nanosec?

[Altera_Forum]

Instead of create_clock you could use  

"derive_pll_clocks -create_base_clocks" With this Timequest should read the values from the PLL and SOPC.

[Altera_Forum]

Hi, 

 But I am not using the pll. I was able to download the program in the board and run it with the negative slack removal values itself.  What are these values important for ?Can anyone explain?

[Altera_Forum]

Timequest estimates timing values for corner cases (at least it should if configured correctly).  

So if your timing fails, it will fail at -40°C or at 100°C (or whatever corner case is defined). It will probably work on your desk, but when deployed to the field it might fail occasionally, or regularly, depending on the amount of bad luck you have.

[Altera_Forum]

Hey thnks mcr42.. 

 But can you explain what in specific is worst case slack for recovery and removal.The one which I am getting as negative in this design are   Worst case slack for: altera reserved tck : removal  Design wide TNS :altera reserved tck :removal  What are the removal and the recovery timings for ?I am aware with the setup and the hold timings.  Thanks!!!

[Altera_Forum]

Recovery and removal are basically the same as setup and hold, but for asynchronous signals. (At least that's what I learned in my Time Quest lesson, someone correct me if i'm wrong). 

 I also learned, that you normally don't care about altera_reserved_*, as there's nothing you can do about it.

[Altera_Forum]

Is the altera_reserved_clk associated with the jtag clk.Because I didnt design it while building the system with SOPC builder.I use only one clk at 50 Mhz. 

But I dont know what is this other clk for?  I am in the process of reading all the documentation for timing. And it actually is not affecting my design I could successfully download the design and run the code in my hardware.  Thanks Again

[Altera_Forum]

altera_reserved_tck is the JTAG clock and it is present in your system if you use the Nios II debugger, JTAG UART, Signaltap II, etc... 

 If you select the failing path as shown in Timequest and copy and paste it into a post you'll probably get better information out of us....

[Altera_Forum]

Hi, 

I am posting the failing path which is in red here.  Slow 1200 mV OC model Removal altera_reserved_tck  Slack : -2.318  from node: altera_reserved_tck  to node : pzdyqx: nabboc|pzdyqx_impl: pzdyqx_impl_inst|FNUJ6967  latch clk : altera_reserved_tck  launch clk : altera_reserved_tck  0.000 clk skew: 8.978 data delay: 6.831   -------------same format as above-----------  Worst case timing paths:  -0.931  altera_reserved_tck  pzdyqx: nabboc|pzdyqx_impl: pzdyqx_impl_inst|FNUJ6967  altera_reserved_tck  altera_reserved_tck  0.000 4.333 3.486  Summary:  altera_reserved_tck slack: -0.931 end point TNS :-0.931  Is this the information which was wanted?  The warnings are:   Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)  Critical Warning: From altera_reserved_tck (Fall) to altera_reserved_tck (Rise) (setup and hold)  Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)  Critical Warning: From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)  Critical Warning: From sopc_clk (Rise) to sopc_clk (Rise) (setup and hold)  Critical Warning: From sopc_clk (Fall) to sopc_clk (Rise) (setup and hold)  Critical Warning: From sopc_clk (Rise) to sopc_clk (Fall) (setup and hold)  System:    Info: SRAM Object File D:/altera_VIP/Altera_Demofiles/niosII_hw_dev_tutorial/niosII_hw_dev_tutorial/nios2_quartus2_project_time_limited.sof contains time-limited megafunction that supports OpenCore Plus feature -- Vendor: 0x6AF7, Product: 0x00A2 Info: Started Programmer operation at Thu Apr 07 16:50:34 2011 Error: Can't access JTAG chain Error: Operation failed Info: Ended Programmer operation at Thu Apr 07 16:50:35 2011 Info: Started Programmer operation at Thu Apr 07 16:50:42 2011 Info: Configuring device index 1 Info: Device 1 contains JTAG ID code 0x020F70DD Info: Configuration succeeded -- 1 device(s) configured Info: Successfully performed operation(s) Info: Ended Programmer operation at Thu Apr 07 16:50:49 2011  There I saw that there are 2 errors    Regards  Sneha

[Altera_Forum]

That path is the open core plus logic. I have filled a bug against that already since it should constrain itself and since it operates on the slow JTAG clock you can safely ignore it. So if the only failing paths have names like this: 

 pzdyqx: nabboc|pzdyqx_impl: pzdyqx_impl_inst|FNUJ6967   you can ignore those. So the reason why you are seeing failures is that the logic isn't constrained and not necessarily true failing paths. Unfortunately those are randomized names so you can't add in your own constrains easily. If you were not expecting open core logic in your system then I would look at your licenses and compare against the IP you are using. When you don't have a valid license for an IP block that supports OCP you'll be able to use it in tethered mode (which uses that logic that is showing up in the failing path).

[Altera_Forum]

Thanks BadOmen, 

 May be that is the reason I could download the code in the Altera board and also debug the software.  The board has been given by university for development purposes and I downloaded the NIOS II and Quartus from the site of Altera.  Its a real useful piece of information for me.  Special Thanks!!  Bye

[Altera_Forum]

HI, 

 In the same tutorial I was able to run the code on the leds but the software does not respond to the lcd or the 7 segment display on the board.I dont see the output there though I can see them on the console while debugging  Can anyone tell why is this happening? I am using cyclone3 development board.