power failure interrupt on NIOS 2

[Altera_Forum]

HI, 

  I am busy with a design of an embedded system with Altera Cyclones with NIOS 2 and a LPC2106 ARM cpu. Have implemented RTC with battery backup, nonvolatile 32kB sram (simtek), a LTC2901 reset controller and a double window watchdog timer in a ATtiny11. I also want to implement a power failure interrupt to the NIOS 2 cpu and the LPC2106 arm. Questions: 1-which interrupt should i use on the NIOS2 and the LPC for power faillure??, i cannot find the equivalent of the NMI interrupt as on the old Z80... 2-How can i prevent garbling up the data during writes to the nonvolatile sram when a power faillure hits??  regards  Ron Proveniers www.info-trade.nl

[Altera_Forum]

We use a Simtek part that has a shadow RAM/EEPROM in it. When power is applied to the part, the contents of the EEPROM are transfered to the RAM. During normal operation you use it just like RAM. When power is removed, the part senses this and transfers the RAM data to the EEPROM. All you need is an external CAP (besides VDD) that keeps the power on the chip active long enough for the transfer. It seems kind of scary, but we have found this device very reliable. If you don't trust the automatic transfers, the part supports the transfers under software control. 

 With this part, there is no need for a low power interrupt handler for our NVM. However, you may have other cleanup activites that need to be done besides the NVM. Your question is valid and I'm also interested in the best way to handle power down conditions.

[Altera_Forum]

Ron, 

 I was playing with the SOPC builder when I remembered that you can have the PIO generate an IRQ. I instansiated one line as an input only and enabled the gen irq + edge triggered irq (input options). Looks like it works, but I don't think there is an equivalent NMI.   Anyone: since the documents state that the IRQs priorities are software controlled, do the IRQ numbers mean anything in the SOPC builder? In another words does IRQ0 have a higher hardware priority than IRQ5?  Rick

[Altera_Forum]

Rick,  

 Short answer: if you use the built-in interrupt support, then ues, irq0 is higher priority than irq5.  Longer answer: The hardware no longer cares -- interrupt behavior is entirely under software control. I don't have the code in front of me, but I think the way the default Nios II ISR handler works is to loop through pending interrupts, lowest ISR number first. During this time, lower priority interrupts are disabled using a CPU register.... the upside to this is that you can change this code if you're adventurous to meet exact system needs.

[Altera_Forum]

By default, the software looks for the highest priority interrupt which is pending and handles that. All interrupts are disabled while it is searching for that interrupt. 

 A low priority interrupt can choose to enable higher priority interrupts while it is handled (using the function alt_irq_interruptible), but this is only of benefit to slow interrupt handlers (those which take more than 50 cycles or so).   If you call alt_irq_interruptable from a fast interrupt handler (as interrupt handlers should be) then this will result in a longer maximum interrupt latency.