problem about SOPC user-define peripheral

Altera_Forum · ‎04-26-2011

I am using SOPC Builder to make an user-define peripheral to scan eight 8-segment LED nixietube.

this is the Hardware decription below:


module Display(clk,data,addr,read_en,write_en,data_out,seg,lbit);
input clk;
input read_en,write_en;
input data;
input addr;
output  seg;
output  lbit;
output data_out;
reg data_in;
reg seg;
reg lbit;
regdata_out;
reg state;
parameter S0 = 1, S1 = 2, S2 = 4,S3 = 8, S4 = 16,S5 = 32, S6 = 64, S7 = 128;
reg clk_div;
initial 
begin 
data_in=249;
data_in=164;
data_in=255;
data_in=255;
data_in=255;
data_in=255;
data_in=255;
data_in=255;
state=S0;
clk_div=0;
end
always @ (state) begin
      case (state)
         S0:begin
            lbit = 254;
                seg = data_in;
               end
         S1:begin
            lbit = 253;
                seg = data_in;
                end
         S2:begin
            lbit = 255-S2;
                seg = data_in;
                end
            S3:begin
            lbit = 255-S3;
                seg = data_in;
                end
         S4:begin
            lbit = 255-S4;
                seg = data_in;
                end
         S5:begin
            lbit = 255-S5;
                seg = data_in;
                end
            S6:begin
            lbit = 255-S6;
                seg = data_in;
                end
         S7:begin
            lbit = 255-S7;
                seg = data_in;
                end  
         endcase        
   end
 
 always @ (posedge clk ) begin
      
        if(clk_div>50_000)begin
        clk_div=0;
           
     
     case (state)
      S0:
         state <= S1;
        S1:
         state <= S2;
        S2:
        state <= S3;
        S3:
         state <= S4;
        S4:
         state <= S5;
        S5:
        state <= S6;
        S6:
         state <= S7;
        S7:
         state <= S0;          
      endcase
        end
        else
        clk_div=clk_div+1;
        
         if(write_en)begin
        //write regs
        case (addr)
      0001:
         data_in <= data;
        0010:
         data_in <= data;
        0011:
         data_in <= data;
        0100:
         data_in <= data;
        0101:
         data_in <= data;
        0110:
         data_in <= data;
        0111:
         data_in <= data;
        0100:
         data_in <= data;
      default:
             data_in <= data_in;
      endcase
        end
        if(read_en) begin
        case (addr)
      0001:
         data_out <= data_in;
        0010:
         data_out <= data_in;
        0011:
         data_out <= data_in;
        0100:
         data_out <= data_in;
        0101:
         data_out <= data_in;
        0110:
         data_out <= data_in;
        0111:
         data_out <= data_in;
        0100:
         data_out <= data_in;
      default:
             data_out <= data_in;
      endcase
        end
        
      
        end
        
endmodule

the initial display is "1" on the first bit and "2" the 2nd bit

this is the configuration :

http://img.ph.126.net/ZD_yXFCIY6AtMj75ZRxGwg==/3736298840857749227.png

http://img.ph.126.net/00UNXKOVQ0JIQprmfmtG_w==/3736298840857749213.png http://img116.ph.126.net/1-zejQOEktieV5jaHM5D_A==/716916765684060417.png

when I debug this Software in Eclipse，

# include  <stdio.h># include <io.h>
# include "system.h"
int main()
{
    printf("Hello Jack");
    IOWR_8DIRECT(DISPLAY_0_BASE,0x30,15);
    IOWR(DISPLAY_0_BASE,0x30,5); //display
    
    return 0;
}

This is the memory when I debug:

display_0_base=0x0

http://img.ph.126.net/hsgeXNWqdqjOCDI7WxyG9w==/1529816498423086278.jpg

when the software running, I can get the "hello Jack". but the memory doesn`t change. The display doesn`t change either.

So where is the problem....Please Give me any Hint^_^

Altera_Forum · ‎04-26-2011

What stands out is that your are trying to access offset 0x30 meanwhile your component only has a span of 16 bytes. Also when you are doing your address decode you are using decimal like 0010 for example instead of binary 4'b0010.

I'm not quite following what you are trying to do but if your statemachine is supposed to be linear why not just make that a counter? Then decode the counter values independently. Split your read/write logic away from your statemachine (counter) so that you are not attempting to do everything from within a single always block. It'll be much easier to understand and probably faster and smaller in terms of the hardware that gets synthesized.

Altera_Forum · ‎04-27-2011

Thank you, I find my mistake