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sdram timing constraints questions

Altera_Forum
Honored Contributor II
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hi  

in BeMicroM10 full_design example projects , it use ISSI IS42S16400J as sdram. 

https://cloud.altera.com/devstore/platform/15.1.0/nios-ii-full-featured-reference-design-bemicro/ 

the nios system clk is 50M hz, and the clk fpga give to the sdram is 50Mhz -90 degree phase shift 

the sdc file contain the follows: 

 

 

set_multicycle_path -from SDRAM_CLK -to [get_ports {SDRAM_DQ[0] .......}] -start -setup 2 

set_multicycle_path -from SDRAM_CLK -to [get_ports {SDRAM_DQ[0] SDRAM_DQ[1] ......-start -hold 1 

 

set_input_delay -clock SDRAM_CLK -clock_fall -max 5.4 [get_ports {SDRAM_DQ[0].....}] 

set_input_delay -clock SDRAM_CLK -clock_fall -min 2.7 [get_ports {SDRAM_DQ[0] .....}] 

 

 

i have several questions: 

1. why the set_input_delay use falling edge? isn't the sdram should be rising edge Synchronous? 

2. because the 20ns clk period is long enough, then i change the phase shift from -90 degree to 144 degree, and i delete the set_multicycle_path, the the "download elf failed" error shows. 

i check the in the eclipse, the timestamp and sysid can be read, so i think the elf file can not be written into the sdram, it must be the timing problem. 

why this happen? it seems like i must use the set_multicycle_path even i have a bigger clk period.
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