Reconfigure FPGA from USB-Blaster on a running HPS system

[Altera_Forum]

I'm developing for the terasic DE0-Nano-SoC Cyclone V kit. 

 The chip must be configured before the HPS can boot, right? I can boot the device and run linux from an SD-card (which also configures the FPGA). I may, apparently, reconfigure the device later with USB-Blaster/JTAG, and it *seems* the linux system is still running after. How is that possible? I thought the FPGA reconfiguration also reconfigured the HPS part?

[Altera_Forum]

The sd card root did nit configure the hps part.

[Altera_Forum]

Is the preloader and dts that configure the hps

[Altera_Forum]

Yes, I am aware that it is the preloader (which happens to be on the SD-card as well) that configures the HPS. My question is that it is possible to reconfigure the FPGA while the HPS is up and running. To me that is somewhat unexpected, since reconfiguration is a low-level action. I'd expect severe side-effects. So is it safe to do?

[Altera_Forum]

I think possible sd hps and fpga coulb be boot up independently or boot from hps first.

[Altera_Forum]

--- Quote Start ---  Yes, I am aware that it is the preloader (which happens to be on the SD-card as well) that configures the HPS. My question is that it is possible to reconfigure the FPGA while the HPS is up and running. To me that is somewhat unexpected, since reconfiguration is a low-level action. I'd expect severe side-effects. So is it safe to do?  --- Quote End ---    I know that my HPS resets whenever I debug the FPGA independently, and I know that there is a recommendation NOT to reset the FPGA unless the AXI buses and associated memory interfaces are first disabled. I think this is a great question for people who have done this before...I sure haven't.  I have loaded an FPGA image in from Linux, and the process is discussed on RocketBoards, http://rocketboards.org/foswiki/documentation/gsrd131programmingfpga#fpga_configuration_from_linux, but this is not dynamic reconfiguration. I don't see why one couldn't try reversing the programming process and see if it allows for dynamic reloads, though! I can't see a reason why not unless the FPGA kernel driver dies.