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write array of a data to sdram from nios using IOWR

Honored Contributor II

Hi! I have a problem with writing data to sdram from nios using IOWR function. I have next code  

for(i = 0; i < 500; i++) { 

IOWR(DRAM_BASE + i, 0, i); 

printf("0x0%x\n", DRAM_BASE + i); 


Sdram is 64 MB. So, first time data is wrinting fine, but problem appers since 452 iteration. I don't know how to fix it problem, can anybody help, maybe i don't undestand how works IOWR function. 


output is  


452 Iteration 



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3 Replies
Honored Contributor II

were you able to debug it?

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Honored Contributor II


I think you might be mixing things up here. 

IOXXX functions are ment for accessing FPGA components that are mapped into the memory space of the nios processor. 

Typically they are the result of a QSYS design were you included PIO or other blocks into the adress space of your processor. 

If you want to access your SDRAM you could use a C/C++ pointer. 

Be carefull when writing into your SDRAM at random spaces, you might destroy your program your heap or your stack. 

If you do then your program will hang. 

Best Regards, 

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Honored Contributor II

When accessing memory that the is used for code with the cache bypassing macros you have to be careful of cache coherency issues. This is usually easier to explain with an example so here goes: 


1) Nios is running some code that allocated a buffer using malloc 

2) Code writes some temporary data to the buffer from step# 1 

3) Code frees the buffer that was allocated in step# 1 

4) Code malloc some more memory and happens to get the same memory as step# 1 

5) Code attempts to perform cache bypassing writes to the buffer from step# 4, you now have a cache coherency issue because memory location being written to is also cached 


To make sure it's safe to perform cache bypassing accesses to the buffer that may be previously cached you should flush those locations first. But it's probably more efficient to write those locations without using cache bypassing macros then flush them out after, especially if the latency between the Nios data master and memory is high. 


If you are wondering why that example is a cache coherency problem, image in step 5 your cache bypassing access was allowed to go through. Eventually the cache line that maps to that location is going to get evicted and overwrite what you previously wrote to memory.
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