I'm using Intel aocl to compile my design for fpga (arria 10) on Intel vLab. The compilations (for both emulation and real hardware) are successful excepts many warnings like "Aggressive compiler optimization: removing unnecessary storage to local memory". The emulation shows my design works well but the running of the hardware (fpga) version does not give me the correct results.
So I was wondering if it is possible for such aggressive optimization to affect the correctness of the calculation.
Any help is appreciated!